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FUJITSU MICROELECTRONICS DATA SHEET
DS07-13734-3Ea
16-bit Microcontroller
CMOS
F2MC-16LX MB90330A Series
MB90333A/F334A/MB90V330A
DESCRIPTION
The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also Mini-HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F2MC family, the instruction set supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURES
* Clock * Built-in oscillation circuit and PLL clock frequency multiplication circuit * Oscillation clock * The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) * Clock for USB is 48 MHz * Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable * Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating VCC = 3.3 V. * The maximum memory space : 16 Mbytes * 24-bit addressing (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://edevice.fujitsu.com/micom/en-support/ "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2007.11
MB90330A Series
(Continued) * Bank addressing * Instruction system * Data types : Bit, Byte, Word and Long word * Addressing mode (23 types) * Enhanced high-precision computing with 32-bit accumulator * Enhanced Multiply/Divide instructions with sign and the RETI instruction * Instruction system compatible with high-level language (C language) and multi-task * Employing system stack pointer * Instruction set symmetry and barrel shift instructions * Program Patch Function (2 address pointer) * 4-byte instruction queue * Interrupt function * Priority levels are programmable * 32 interrupts function * Data transfer function * Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels * DMAC : Maximum 16 channels * Low Power Consumption Mode * Sleep mode (with the CPU operating clock stopped) * Time-base timer mode (with the oscillator clock and time-base timer operating) * Stop mode (with the oscillator clock stopped) * CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) * Watch mode (with 32 kHz oscillator clock and watch timer operating) * Package * LQFP-120P (FPT-120P-M05 : 0.40 mm pin pitch) * LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch) * Process : CMOS technology * Operation guaranteed temperature : - 40 C to + 85 C (0 C to + 70 C when USB is in use)
2
MB90330A Series
INTERNAL PERIPHERAL FUNCTION (RESOURCE)
* I/O port : Max 94 ports * Time-base timer : 1 channel * Watchdog timer : 1 channel * Watch timer : 1 channel * 16-bit reload timer : 3 channels * Multi-functional timer * 16-bit free run timer : 1 channel * Output compare : 4 channels An interrupt request can be output when the 16-bit free-run timer value matches the compare register value. * Input capture : 4 channels Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the input capture data register to the 16-bit free-run timer value to output an interrupt request. * 8/16-bit PPG timer (8-bit x 6 channels or 16-bit x 3 channels) the period and duty of the output pulse can be set by the program. * 16-bit PWC timer : 1 channel Timer function and pulse width measurement function * UART : 4 channels * Full-duplex double buffer (8-bit length) * Asynchronous transfer or clock-synchronous serial (Extended I/O serial) transfer can be set. * Extended I/O serial interface : 1 channel * DTP/External interrupt circuit (8 channels) * Activate the extended intelligent I/O service by external interrupt input * Interrupt output by external interrupt input * Delay interrupt output module * Output an interrupt request for task switching * 8/10-bit A/D converter : 16 channels * 8-bit resolution or 10-bit resolution can be set. * USB : 1 channel * USB function (correspond to USB Full Speed) * Full Speed is supported/Endpoint are specifiable up to six. * Dual port RAM (The FIFO mode is supported). * Transfer type : Control, Interrupt, Bulk, or Isochronous transfer possible * USB Mini-HOST function * I2C* Interface : 3 channels * Supports Intel SM bus standard and Phillips I2C bus standards * Two-wire data transfer protocol specification * Master and slave transmission/reception * : I2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
3
MB90330A Series
PRODUCT LINEUP
Part number Type ROM capacity RAM capacity Emulator-specific power supply * MB90V330A For evaluation No 28 Kbytes Yes MB90F334A Built-in Flash memory 384 Kbytes 24 Kbytes MB90333A Built-in MASK ROM 256 Kbytes 16 Kbytes
CPU functions
Number of basic instructions : 351 instructions Minimum instruction execution time : 41.6 ns/at oscillation of 6 MHz (When 4 times are used : Machine clock of 24 MHz) Addressing type : 23 types Program Patch Function : For 2 address pointers Maximum memory space : 16 Mbytes I/O Ports (CMOS) 94 ports Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable It can also be used for I/O serial Built-in special baud-rate generator Built-in 4 channels 16-bit reload timer operation Built-in 3 channels 16-bit free run timer x 1 channel Output compare x 4 channels Input capture x 4 channels 8/16-bit PPG timer (8-bit mode x 6 channels, 16-bit mode x 3 channels) 16-bit PWC timer x 1 channel 16 channels (input multiplex) 8-bit resolution or 10-bit resolution can be set. Conversion time : 7.16 s at minimum (24 MHz machine clock at maximum) 8 channels Interrupt factor : "L""H" edge/"H""L" edge/"L" level/"H" level selectable 3 channels 1 channel 1 channel USB function (correspond to USB Full Speed) USB Mini-HOST function For multi-bus/non-multi-bus 16 ports (excluding UTEST and I/O for I2C) Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/ Watch mode CMOS 3.3 V 0.3 V (at maximum machine clock 24 MHz)
Ports
UART
16-bit reload timer
Multi-functional timer
8/10-bit A/D converter
DTP/External interrupt I2C Extended I/O serial interface USB External bus interface Withstand voltage of 5 V Low Power Consumption Mode Process Operating voltage
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
4
MB90330A Series
PACKAGES AND PRODUCT MODELS
Package FPT-120P-M05 (LQFP-0.40 mm) FPT-120P-M21 (LQFP-0.50 mm) PGA-299C-A01 (PGA) : Yes x : No Note : For detailed information on each package, refer to " PACKAGE DIMENSIONS". x x MB90333A MB90F334A MB90V330A x x
5
6
PIN ASSIGNMENT
MB90330A Series
P30/A00/TIN1 P31/A01/TOT1 P32/A02/TIN2 P33/A03/TOT2 P34/A04 P35/A05 P36/A06 P37/A07 P40/A08/TIN0 P41/A09/TOT0 P42/A10/SIN0 P43/A11/SOT0 X0A X1A VCC VSS P44/A12/SCK0 P45/A13/SIN1 P46/A14/SOT1 P47/A15/SCK1 P60/INT0 P61/INT1 P62/INT2/SIN P63/INT3/SOT P64/INT4/SCK P65/INT5/PWC P66/INT6/SCL0 P67/INT7/SDA0 P90/SIN2 P91/SOT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(TOP VIEW)
(FPT-120P-M05 / FPT-120P-M21)
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RST MD0 MD1 MD2 P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE HCON VCC HVP HVM VSS VCC DVP DVM VSS UTEST PB6/PPG5 PB5/PPG4 PB4 PB3/SDA2 PB2/SCL2 PB1/SDA1 PB0/SCL1 PA7/OUT3 PA6/OUT2 PA5/OUT1
P92/SCK2 P93/SIN3 P94/SOT3 P95/SCK3 P96/ADTG/FRCK AVCC AVRH AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 VSS P80/AN8 P81/AN9 P82/AN10 P83/AN11 P84/AN12 P85/AN13 P86/AN14 P87/AN15 PA0/IN0 PA1/IN1 PA2/IN2 PA3/IN3 PA4/OUT0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
P27/A23/PPG3 P26/A22/PPG2 P25/A21/PPG1 P24/A20/PPG0 P23/A19 P22/A18 P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 X0 X1 VSS VCC P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 P57/CLK P56/RDY
MB90330A Series
PIN DESCRIPTION
Pin no. 108, 107 13, 14 90 Pin name X0, X1 X0A, X1A RST P00 to P07 93 to 100 AD00 to AD07 D00 to D07 H I/O Circuit type* A A F Function Terminals to connect the oscillator. When connecting an external clock, leave the X1 pin side unconnected. 32 kHz oscillation terminals. External reset input pin. General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.) Function as an I/O pin for the low-order external address and data bus in multiplex mode. Function as an output pin for the low-order external data bus in nonmultiplex mode. General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) H AD08 to AD11 D08 to D11 Function as an I/O pin for the high-order external address and data bus in multiplex mode. Function as an output pin for the high-order external data bus in nonmultiplex mode. General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) H AD12 to D15 D12 to D15 P20 to P23 113 to 116 A16 to A19 A16 to A19 D Function as an I/O pin for the high-order external address and data bus in multiplex mode. Function as an output pin for the high-order external data bus in nonmultiplex mode. This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins. When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins. (Continued)
P10 to P13 101 to 104
P14 to P17 109 to 112
7
MB90330A Series
Pin no.
Pin name
I/O Circuit type*
Function This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.
P24 to P27 A20 to A23 A20 to A23 PPG0 to PPG3 P30 1 A00 TIN1 P31 2 A01 TOT1 P32 3 A02 TIN2 P33 4 A03 TOT2 5 to 8 P34 to P37 A04 to A07 P40 9 A08 TIN0 P41 10 A09 TOT0 P42 11 A10 SIN0 P43 12 A11 SOT0 P44 17 A12 SCK0 G G G G G D D D D D
117 to 120
D
When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins. When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins. Function as ch.0 to ch.3 output pins for the 8-bit PPG timer. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.1. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.1. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.2. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.2. General purpose input/output port. Function as the external address pin in non-multi-bus mode. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as an event input pin for 16-bit reload timer ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as the output pin for 16-bit reload timer ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data input pin for UART ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data output pin for UART ch.0. General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a clock I/O pin for UART ch.0. (Continued)
8
MB90330A Series
Pin no.
Pin name P45
I/O Circuit type* G
Function General purpose input/output port. Function as the external address pin in non-multi-bus mode. Function as a data input pin for UART ch.1. General purpose input/output port.
18
A13 SIN1 P46
19
A14 SOT1 P47
G
Function as the external address pin in non-multi-bus mode. Function as a data output pin for UART ch.1. General purpose input/output port.
20
A15 SCK1 P50 ALE P51 RD P52
G
Function as the external address pin in non-multi-bus mode. Function as a clock I/O pin for UART ch.1. General purpose input/output port. Function as the address latch enable signal pin in external bus mode. General purpose input/output port. Function as the read strobe output pin in external bus mode. General purpose input/output port. Function as the data write strobe output pin on the lower side in external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". General purpose input/output port. Function as the data write strobe output pin on the higher side in bus width 16-bit external bus mode. This pin functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". General purpose input/output port. Function as the hold request input pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". General purpose input/output port. Function as the hold acknowledge output pin in external bus mode. This pin functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". General purpose input/output port. Function as the external ready input pin in external bus mode. This pin functions as a general-purpose I/O port when the RYE bit in the EPCR register is "0". General purpose input/output port. Function as the machine cycle clock output pin in external bus mode. This pin functions as a general-purpose I/O port when the CKE bit in the EPCR register is "0". General purpose input/output port. (With stand voltage of 5 V) Function as external interrupt ch.0 and ch.1 input pins. (Continued) 9
81 82
L L
83
WRL P53
L
84
WRH P54
L
85
HRQ P55
L
86
HAK P56
L
91
RDY P57
L
92
CLK P60, P61 INT0, INT1
L
21, 22
C
MB90330A Series
Pin no.
Pin name P62
I/O Circuit type* C
Function General purpose input/output ports. (Withstand voltage of 5 V) Function as an external interrupt ch.2 input pin. Extended I/O serial interface data input pin. General purpose input/output port. (Withstand voltage of 5 V)
23
INT2 SIN P63
24
INT3 SOT P64
C
Function as an external interrupt ch.3 input pin. Extended I/O serial interface data output pin. General purpose input/output port. (Withstand voltage of 5 V)
25
INT4 SCK P65
C
Function as an external interrupt ch.4 input pin. Extended I/O serial interface clock input/output pin. General purpose input/output port. (Withstand voltage of 5 V)
26
INT5 PWC P66 INT6 SCL0 P67
C
Function as an external interrupt ch.5 input pin. Function as the PWC input pin. General purpose input/output port. (Withstand voltage of 5 V) Function as an external interrupt ch.6 input pin. Function as the ch.0 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as an external interrupt ch.7 input pin. Function as the ch.0 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. Function as input pins for analog ch.0 to ch.7. General purpose input/output port. Function as input pins for analog ch.8 to ch.15. General purpose input/output port. Function as a data input pin for UART ch.2. General purpose input/output port. Function as a data output pin for UART ch.2. General purpose input/output port. Function as a clock I/O pin for UART ch.2. General purpose input/output port. Function as a data input pin for UART ch.3. General purpose input/output port. Function as a data output pin for UART ch.3. General purpose input/output port. Function as a clock I/O pin for UART ch.3. General purpose input/output port. (Withstand voltage of 5 V) Function as the external trigger input pin when the A/D converter is being used. Function as the external clock input pin when the free-run timer is being used. (Continued)
27
C
28
INT7 SDA0
C
39 to 46 48 to 55 29 30 31 32 33 34
P70 to P77 AN0 to AN7 P80 to P87 AN8 to AN15 P90 SIN2 P91 SOT2 P92 SCK2 P93 SIN3 P94 SOT3 P95 SCK3 P96 ADTG FRCK
I I D D D D D D
35
C
10
MB90330A Series
(Continued) Pin no. Pin name PA0 to PA3 IN0 to IN3 PA4 to PA7 OUT0 to OUT3 PB0 64 SCL1 PB1 65 SDA1 PB2 66 SCL2 PB3 67 68 69, 70 71 73 74 77 78 80 36 37 38 87 to 89 15 75 79 105 16 47 72 76 106 SDA2 PB4 PB5, PB6 PPG4, PPG5 UTEST DVM DVP HVM HVP HCON AVcc AVRH AVss MD2 to MD0 Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss C C D C K K K K E J B C C C I/O Circuit type* C C Function General purpose input/output port. (Withstand voltage of 5 V) Function as the input capture ch.0 to ch.3 trigger inputs. General purpose input/output port. (Withstand voltage of 5 V) Function as the output compare ch.0 to ch.3 event output pins. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.1 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.1 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.2 clock I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) Function as the ch.2 data I/O pin for the I2C interface. Set port output to High-Z during I2C interface operations. General purpose input/output port. (Withstand voltage of 5 V) General purpose input/output port. Function as ch.4 and ch.5 output pins for the 8-bit PPG timer. USB test pin. Connect this to a pull-down resistor during normal usage. USB function D- pin. USB function D+ pin. USB Mini-HOST D- pin. USB Mini-HOST D+ pin. External pull-up resistor connect pin. A/D converter power supply pin. A/D converter external reference power supply pin. A/D converter power supply pin. Operation mode select input pin. Power supply pin. Power supply pin. Power supply pin. Power supply pin. Power supply pin (GND). Power supply pin (GND). Power supply pin (GND). Power supply pin (GND). Power supply pin (GND).
56 to 59 60 to 63
* : For circuit information, refer to " I/O CIRCUIT TYPE". 11
MB90330A Series
I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * High-rate oscillation feedback resistor, approx.1 M * Low-rate oscillation feedback resistor, approx.10 M * With standby control CMOS hysteresis input CMOS hysteresis input
Clock input
X1A X0 X0A
Standby control signal
B
C
* CMOS hysteresis input * N-ch open drain output
N-ch
Nout
CMOS hysteresis input Standby control signal D
P-ch Pout
N-ch
Nout
CMOS hysteresis input Standby control signal E
P-ch Pout
* CMOS output * CMOS hysteresis input (With input interception function at standby) Notes : * Share one output buffer because both output of I/O port and internal resource are used. * Share one input buffer because both input of I/O port and internal resource are used. CMOS output
N-ch
Nout
F
R
CMOS hysteresis input with pull-up resistor
CMOS hysteresis input (Continued)
12
MB90330A Series
Type G
P-ch
Circuit
Remarks * CMOS output * CMOS hysteresis input (With input interception function at standby) With open drain control signal
Pout
Open drain control signal
N-ch
Nout
CMOS hysteresis input Standby control signal H
CTL R P-ch Pout
* CMOS output * CMOS input (With input interception function at standby) * With input pull-up register control
N-ch
Nout
CMOS input Standby control signal I * CMOS output * CMOS hysteresis input (With input interception function at standby) * Analog input (The A/D converter analog input is enabled when the corresponding bit in the analog input enable register (ADER) is 1.) Notes: * Because the output of the I/O port and the output of internal resources are used combinedly, one output buffer is shared. * Because the input of the I/O port and the input of internal resources are used combinedly, one input buffer is shared. A/D converter (AVRH) voltage input pin
P-ch P-ch N-ch N-ch
P-ch
Pout
N-ch
Nout
CMOS hysteresis input Standby control signal A/D converter analog input
J
AVRH input A/D converter analog input enable signal (Continued) 13
MB90330A Series
(Continued) Type K D + input D - input
D+
Circuit USB I/O pin
Remarks
Differential input
D-
Full D + output Full D - output Low D + output Low D - output Direction Speed
L
P-ch Pout
* CMOS output * CMOS input * With standby control
N-ch
Nout
CMOS input Standby control signal
14
MB90330A Series
HANDLING DEVICES
1. Preventing latch-up and turning on power supply
Latch-up may occur on CMOS IC under the following conditions: * If a voltage higher than VCC or lower than VSS is applied to input and output pins. * A voltage higher than the rated voltage is applied between VCC pin and VSS pin. * If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open.
3. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS.
4. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. * Using external clock
X0
OPEN
X1
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC pin and VSS pin near this device.
15
MB90330A Series
6. About Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu Microelectronics will not guarantee results of operations if such failure occurs.
8. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching.
9. When the dual-supply is used as a single-supply device
If you are using only a single-system of the MB90330A series that come in the dual-system product, use it with X0A = VSS : X1A = OPEN.
10. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
16
MB90330A Series
BLOCK DIAGRAM
X0, X1 X0A,X1A RST MD0 to MD2
Clock control circuit Interrupt controller RAM ROM
F2MC-16LX CPU
8/16-bit PPG timer ch.0 to ch.5* Input capture ch.0 to ch.3
PPG0 to PPG5
SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3 SCL0 to SCL2 SDA0 to SDA2 AVCC AVRH AVSS AN0 to AN15 ADTG TOT0 to TOT2 TIN0 to TIN2 DVP DVM HVP HVM HCON UTEST INT0 to INT7
IN0 to IN3
UART/SIO ch.0 to ch.3
Internal data bus
I2C ch.0 to ch.2
16-bit free-run timer
FRCK
8/10-bit A/D converter
Output compare ch.0 to ch.3 16-bit PWC
OUT0 to OUT3
16-bit reload timer ch.0 to ch.2 USB (Function) (Mini-HOST)
External interrupt
PWC SIN SOT SCK
SIO DMAC
I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
P00 P07
P10 P17
P20 P27
P30 P37
P40 P47
P50 P57
P60 P67
P70 P77
P80 P87
P90 P96
PA0 PB0 PA7 PB6
* : Channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, refer to " PIN ASSIGNMENT" and " PIN DESCRIPTION". Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
17
MB90330A Series
MEMORY MAP
Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90F334A
ROM (FF bank) ROM (FE bank) ROM (FD bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH ROM (FB bank) ROM (FA bank) ROM (F9 bank) FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90333A
ROM (FF bank) ROM (FE bank) ROM (FD bank)
ROM (FB bank)
00FFFFH 008000H 007FFFH 007900H 007100H
ROM (image of FF bank) Peripheral area
00FFFFH 008000H 007FFFH 007900H
ROM (image of FF bank) Peripheral area
00FFFFH 008000H 007FFFH 007900H
ROM (image of FF bank) Peripheral area
006100H 004100H RAM area (28 Kbytes) 000100H 0000FBH Peripheral area 000000H 000000H Register 000100H 0000FBH Peripheral area 000000H RAM area (24 Kbytes) Register 000100H 0000FBH Peripheral area RAM area (16 Kbytes) Register
Memory map of MB90330A series (1/3)
18
MB90330A Series
Internal ROM external bus mode (with ROM mirror function)
MB90V330A
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H External area 00FFFFH 008000H 007FFFH 007900H External area 007100H 006100H 00FFFFH 008000H 007FFFH 007900H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
MB90F334A
FFFFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) FF0000H FEFFFFH FE0000H FDFFFFH
MB90333A
ROM (FF bank) ROM (FE bank) ROM (FD bank)
*1
ROM (FB bank) ROM (FA bank) ROM (F9 bank)
FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H
*2
ROM (FB bank)
*2
External area External area
*1
External area 00FFFFH 008000H 007FFFH 007900H External area 004100H
External area
ROM (image of FF bank) Peripheral area
ROM (image of FF bank) Peripheral area
ROM (image of FF bank) Peripheral area
External area
RAM area (28 Kbytes) 000100H 0000FBH Peripheral area 000000H 000000H Register 000100H 0000FBH
RAM area (24 Kbytes) Register 000100H 0000FBH Peripheral area 000000H
RAM area (16 Kbytes) Register
Peripheral area
*1 : In the area of F80000H to F8FFFFH and FC0000H to FCFFFFH at MB90F334A, a value of "1" is read at read operating. *2 : In the area of FA0000H to FAFFFFH and FC0000H to FCFFFFH at MB90333A, a value of "1" is read at read operating.
Memory map of MB90330A series (2/3)
19
MB90330A Series
External ROM external bus mode
MB90V330A
FFFFFFH FFFFFFH
MB90F334A
FFFFFFH
MB90333A
External area
External area
External area
008000H 007FFFH 007900H
Peripheral area
008000H 007FFFH 007900H
Peripheral area
008000H 007FFFH 007900H
Peripheral area
External area 007100H 006100H RAM area (28 Kbytes) Register
External area 004100H RAM area (24 Kbytes) 000100H 0000FBH Register 000100H 0000FBH Peripheral area 000000H 000000H
External area
RAM area (16 Kbytes) Register
000100H 0000FBH
Peripheral area 000000H
Peripheral area
Memory map of MB90330A series (3/3) Notes : * When the ROM mirror function register has been set, the mirror image data at higher addresses ("FF8000H to FFFFFFH") of bank FF is visible from the higher addresses ("008000H to 00FFFFH") of bank 00. * The ROM mirror function is effective for using the C compiler small model. * The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. * When the C compiler small model is used, the data table mirror image can be shown at "008000H to 00FFFFH" by storing the data table at "FF8000H to FFFFFFH". Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer.
20
MB90330A Series
F2MC-16L CPU PROGRAMMING MODEL
* Dedicated register
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General purpose register
MSB 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16-bit LSB
* Processor status
Bit 15 PS ILM 13 12 RP 87 CCR 0
21
MB90330A Series
I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H Register abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB DDRB Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 8 Data Register Port 9 Data Register Port A Data Register Prohibited Port B Data Register Port B Direction Register Prohibited DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 ADER0 ADER1 SMR0 SCR0 SIDR0 SODR0 SSR0 UTRLR0 UTCR0 Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 7 Direction Register Port 8 Direction Register Port 9 Direction Register Port A Direction Register Port 4 Output Pin Register Port 0 Pull-up Resistance Register Port 1 Pull-up Resistance Register Analog Input Enable Register 0 Analog Input Enable Register 1 Serial Mode Register 0 Serial Control Register 0 Serial Input Data Register 0 Serial Output Data Register 0 Serial Status Register 0 UART Prescaler Reload Register 0 UART Prescaler Control Register 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (open drain control) Port 0 (PULL-UP) Port 1 (PULL-UP) Port 7, 8, A/D Port 7, 8, A/D 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB R/W R/W Port B Port B - XXXXXXXB - 0 0 0 0 0 0 0B Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - XXXXXXXB XXXXXXXXB
UART0
0 0 0 0 1 0 0 0B Communication 0 0 0 0 0 0 0 0B Prescaler (UART0) 0 0 0 0 - 0 0 0B (Continued)
22
MB90330A Series
Address 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H to 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H
Register abbreviation SMR1 SCR1 SIDR1 SODR1 SSR1 UTRLR1 UTCR1 SMR2 SCR2 SIDR2 SODR2 SSR2 UTRLR2 UTCR2 SMR3 SCR3 SIDR3 SODR3 SSR3 UTRLR3 UTCR3
Register Serial Mode Register 1 Serial Control Register 1 Serial Input Data Register 1 Serial Output Data Register 1 Serial Status Register 1 UART Prescaler Reload Register 1 UART Prescaler Control Register 1 Serial Mode Register 2 Serial Control Register 2 Serial Input Data Register 2 Serial Output Data Register 2 Serial Status Register 2 UART Prescaler Reload Register 2 UART Prescaler Control Register 2 Serial Mode Register 3 Serial Control Register 3 Serial Input Data Register 3 Serial Output Data Register 3 Serial Status Register 3 UART Prescaler Reload Register 3 UART Prescaler Control Register 3 Prohibited
Read/ Write R/W R/W R W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R W R/W R/W R/W
Resource name
Initial Value 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART1
XXXXXXXXB 0 0 0 0 1 0 0 0B
Communication 0 0 0 0 0 0 0 0B Prescaler (UART1) 0 0 0 0 - 0 0 0B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART2 XXXXXXXXB 0 0 0 0 1 0 0 0B Communication 0 0 0 0 0 0 0 0B Prescaler (UART2) 0 0 0 0 - 0 0 0B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART3 XXXXXXXXB 0 0 0 0 1 0 0 0B Communication Prescaler (UART3) 0 0 0 0 - 0 0 0B 0 0 0 0 0 0 0 0B
ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1
DTP/Interrupt Enable Register DTP/Interrupt Source Register Request Level Setting Register Lower Request Level Setting Register Upper A/D Control Status Register Lower A/D Control Status Register Upper A/D Data Register Lower A/D Data Register Upper Prohibited A/D Conversion Channel Selection Register PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register PPG2 Operation Mode Control Register
R/W R/W R/W R/W R/W R/W R/W R/W 8/10-bit A/D Converter PPG ch.0 PPG ch.1 PPG ch.2 8/10-bit A/D Converter DTP/External Interrupt
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 - - - - - 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 1 0 1 XXXB
ADMR PPGC0 PPGC1 PPGC2
R/W R/W R/W R/W
0 0 0 0 0 0 0 0B 0X0 0 0XX1B 0X0 0 0 0 0 1B 0X0 0 0XX1B (Continued) 23
MB90330A Series
Address 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H
Register abbreviation PPGC3 PPGC4 PPGC5 PPG01
Register PPG3 Operation Mode Control Register PPG4 Operation Mode Control Register PPG5 Operation Mode Control Register PPG0 and PPG1 Output Control Register Prohibited PPG2 and PPG3 Output Control Register Prohibited PPG4 and PPG5 Output Control Register Prohibited
Read/ Write R/W R/W R/W R/W
Resource name PPG ch.3 PPG ch.4 PPG ch.5 PPG ch.0/ch.1
Initial Value 0X0 0 0 0 0 1B 0X0 0 0XX1B 0X0 0 0 0 0 1B 0 0 0 0 0 0XXB
PPG23
R/W
PPG ch.2/ch.3
0 0 0 0 0 0 XXB
PPG45
R/W
PPG ch.4/ch.5
0 0 0 0 0 0 XXB
ICS01 ICS23 OCS0 OCS1 OCS2 OCS3 SMCS SDR SDCR PWCSR PWCR DIVR
Input Capture Control Status Register 01 Input Capture Control Status Register 23 Output Compare Control Register ch.0 Lower Output Compare Control Register ch.1 Upper Output Compare Control Register ch.2 Lower Output Compare Control Register ch.3 Upper Serial Mode Control Status Register Serial Data Register Communication Prescaler Control Register PWC Control Status Register PWC Data Buffer Register PWC Dividing Ratio Control Register Prohibited
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Input Capture ch.0/ch.1
0 0 0 0 0 0 0 0B
Input 0 0 0 0 0 0 0 0B Capture ch.2/ch.3 Output Compare ch.0/ch.1 Output Compare ch.2/ch.3 Extended Serial I/O Communication Prescaler 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B XXXX0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0XXX0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit PWC Timer 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - 0 0B 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B 16-bit Reload Timer ch.0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
TMCSR0 TMR0 TMRLR0 TMR0 TMRLR0
Timer Control Status Register 0 16-bit Timer Register 0 Lower 16-bit Reload Register 0 Lower 16-bit Timer Register 0 Upper 16-bit Reload Register 0 Upper
R/W R W R W
24
MB90330A Series
Address 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H to 000085H
Register abbreviation TMCSR1 TMR1 TMRLR1 TMR1 TMRLR1 TMCSR2 TMR2 TMRLR2 TMR2 TMRLR2
Register Timer Control Status Register 1 16-bit Timer Register 1 Lower 16-bit Reload Register 1 Lower 16-bit Timer Register 1 Upper 16-bit Reload Register 1 Upper Timer Control Status Register 2 16-bit Timer Register 2 Lower 16-bit Reload Register 2 Lower 16-bit Timer Register 2 Upper 16-bit Reload Register 2 Upper Prohibited
Read/ Write R/W R W R W R/W R W R W
Resource name
Initial Value 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B
16-bit Reload Timer ch.1
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B
16-bit Reload Timer ch.2
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
ROMM IBSR0 IBCR0 ICCR0 IADR0 IDAR0 IBSR1 IBCR1 ICCR1 IADR1 IDAR1 IBSR2 IBCR2 ICCR2 IADR2 IDAR2
ROM Mirror Function Selection Register I2C Bus Status Register 0 I C Bus Control Register 0 I C Bus Clock Control Register 0 I2C Bus Address Register 0 I2C Bus Data Register 0 Prohibited I C Bus Status Register 1 I C Bus Control Register 1 I C Bus Clock Control Register 1 I C Bus Address Register 1 I C Bus Data Register 1 Prohibited I2C Bus Status Register 2 I C Bus Control Register 2 I C Bus Clock Control Register 2 I C Bus Address Register 2 I C Bus Data Register 2 Prohibited
2 2 2 2 2 2 2 2 2 2 2
W R R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W
ROM Mirror Function Selection Module
- - - - - - 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
I2C Bus Interface ch.0
XX 0 XXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
I2C Bus Interface ch.1
XX 0 XXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
I2C Bus Interface ch.2
XX 0 XXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
25
MB90330A Series
Address 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH to 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH
Register abbreviation TCDT TCCS CPCLR
Register Timer Data Register Lower Timer Data Register Upper Timer Control Status Register Lower Timer Control Status Register Upper Compare Clear Register Lower Compare Clear Register Upper Prohibited
Read/ Write R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
16-bit Free-Run Timer
0 0 0 0 0 0 0 0B 0 - - 0 0 0 0 0B XXXXXXXXB XXXXXXXXB
DCSR DSRL DSRH PACSR DIRR LPMCR CKSCR
DMA Descriptor Channel Specification Register DMA Status Register Lower DMA Status Register Upper Program Address Detection Control Status Register Delay Interruption Factor Generation/ Release Register Low Power Consumption Mode Control Register Clock Selection Register Prohibited
R/W R/W R/W R/W R/W R/W R/W Address Match Detection Delay Interrupt Low Power Consumption Control Circuit Clock DMAC
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
DSSR ARSR HACR EPCR WDTC TBTC WTC DERL DERH FMCS
DMA Stop Status Register Automatic Ready Function Selection Register External Address Output Control Register Bus Control Signal Selection Register Watchdog Timer Control Register Time-base Timer Control Register Watch Timer Control Register Prohibited DMA Enable Register Lower DMA Enable Register Upper Flash Memory Control Status Register Prohibited
R/W W W W R/W R/W R/W R/W R/W R/W
DMAC
0 0 0 0 0 0 0 0B 0 0 1 1- - 0 0B
External Pin
B 1 0 0 0 1 0 -B
Watchdog Timer Time-base Timer Watch Timer
X - XXX 1 1 1B 1 - - 0 0 1 0 0B 1 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 X 0 0 0 0B
DMAC Flash Memory I/F
(Continued)
26
MB90330A Series
Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H
Register abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 HCNT0 HCNT1 HIRQ HERR HSTATE HFCOMP
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 Host Control Register 0 Host Control Register 1 Host Interruption Register Host Error Status Register Host State Status Register SOF Interrupt FRAME Compare Register Retry Timer Setting Register Host Address Register EOF Setting Register FRAME Setting Register Host Token End Point Register Prohibited
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Interrupt Controller
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B XX 0 1 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
HRTIMER HADR HEOF HFRAME HTOKEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
USB Mini-HOST
0 0 0 0 0 0 0 0B XXXXXX 0 0B X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX 0 0 0B 0 0 0 0 0 0 0 0B 1 0 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued)
UDCC
UDC Control Register
USB Function
27
MB90330A Series
Address 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H
Register abbreviation EP0C EP1C EP2C EP3C EP4C EP5C TMSP UDCS UDCIE EP0IS EP0OS EP1S EP2S EP3S EP4S EP5S EP0DT EP1DT EP2DT EP3DT
Register EP0 Control Register EP1 Control Register EP2 Control Register EP3 Control Register EP4 Control Register EP5 Control Register Time Stamp Register UDC Status Register UDC Interrupt Enable Register EP0I Status Register EP0O Status Register EP1 Status Register EP2 Status Register EP3 Status Register EP4 Status Register EP5 Status Register EP0 Data Register EP1 Data Register EP2 Data Register EP3 Data Register
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W, R R/W R/W R/W, R R/W R R/W, R R R/W, R R R/W, R R R/W, R R R/W, R R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 1 0 0 0 0 0 0B XXXX 0 0 0 0B 0 0 0 0 0 0 0 0B 0 1 1 0 0 0 0 1B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX0 0 0B XX0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 1 0 XXX 1 XXB 0 XXXXXXXB 1 0 0 XX 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
USB Function
28
MB90330A Series
Address 0000F8H 0000F9H 0000FAH 0000FBH 0000FCH to 0000FFH 000100H to #H 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H #H to 0078FFH 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 007908H 007909H 00790AH 00790BH 00790CH to 00790FH
Register abbreviation EP4DT EP5DT
Register EP4 Data Register EP5 Data Register
Read/ Write R/W R/W R/W R/W Prohibited
Resource name
Initial Value XXXXXXXXB
USB Function
XXXXXXXXB XXXXXXXXB XXXXXXXXB
RAM Area Program Address Detection Register ch.0 Lower PADR0 Program Address Detection Register ch.0 Middle Program Address Detection Register ch.0 Upper Program Address Detection Register ch.1 Lower PADR1 Program Address Detection Register ch.1 Middle Program Address Detection Register ch.1 Upper Unused Area PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PPG Reload Register Lower ch.0 PPG Reload Register Upper ch.0 PPG Reload Register Lower ch.1 PPG Reload Register Upper ch.1 PPG Reload Register Lower ch.2 PPG Reload Register Upper ch.2 PPG Reload Register Lower ch.3 PPG Reload Register Upper ch.3 PPG Reload Register Lower ch.4 PPG Reload Register Upper ch.4 PPG Reload Register Lower ch.5 PPG Reload Register Upper ch.5 Prohibited (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection
PPG ch.0 PPG ch.1 PPG ch.2 PPG ch.3 PPG ch.4 PPG ch.5
29
MB90330A Series
(Continued) Address 007910H 007911H 007912H 007913H 007914H 007915H 007916H 007917H 007918H 007919H 00791AH 00791BH 00791CH 00791DH 00791EH 00791FH 007920H 007921H 007922H 007923H 007924H 007925H 007926H 007927H 007928H to 007FFFH * Explanation on read/write R/W : Readable / Writable R : Read only W : Write only * Explanation on initial values 0 : Initial value is "0". 1 : Initial value is "1". X : Initial value is undefined. : Initial value is undefined (None) . : Initial value of this bit is "1" or "0". Note : No I/O instruction can be used for registers located between 007900H and 007FFFH. 30 Register abbreviation IPCP0 IPCP1 IPCP2 IPCP3 OCCP0 OCCP1 OCCP2 OCCP3 DBAPL DBAPM DBAPH DMACS DIOAL DIOAH DDCTL DDCTH Register Input Capture Data Register Lower ch.0 Input Capture Data Register Upper ch.0 Input Capture Data Register Lower ch.1 Input Capture Data Register Upper ch.1 Input Capture Data Register Lower ch.2 Input Capture Data Register Upper ch.2 Input Capture Data Register Lower ch.3 Input Capture Data Register Upper ch.3 Output Compare Register Lower ch.0 Output Compare Register Upper ch.0 Output Compare Register Lower ch.1 Output Compare Register Upper ch.1 Output Compare Register Lower ch.2 Output Compare Register Upper ch.2 Output Compare Register Lower ch.3 Output Compare Register Upper ch.3 DMA Buffer Address Pointer Lower 8-bit DMA Buffer Address Pointer Middle 8-bit DMA Buffer Address Pointer Upper 8-bit DMA Control Register DMA I/O Register Address Pointer Lower 8-bit DMA I/O Register Address Pointer Upper 8-bit DMA Data Counter Lower 8-bit DMA Data Counter Upper 8-bit Prohibited Read/ Write R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMAC Output Compare ch.2/ch.3 Output Compare ch.0/ch.1 Input Capture ch.2/ch.3 Input Capture ch.0/ch.1 Resource name Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
MB90330A Series
INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT 9 instruction Exceptional treatment USB Function1 USB Function2 USB Function3 USB Function4 USB Mini-HOST1 USB Mini-HOST2 I2C ch.0 DTP/External interrupt ch.0/ch.1 I2C ch.1 DTP/External interrupt ch.2/ch.3 I2C ch.2 DTP/External interrupt ch.4/ch.5 PWC/Reload timer ch.0 DTP/External interrupt ch.6/ch.7 Input capture ch.0/ch.1 Reload timer ch.1 Input capture ch.2/ch.3 Reload timer ch.2 Output compare ch.0/ch.1 PPG ch.0/ch.1 Output compare ch.2/ch.3 PPG ch.2/ch.3 UART (Send completed) ch.2/ch.3 PPG ch.4/ch.5 UART (Reception completed) ch.2/ch.3 A/D converter/Free-run timer UART (Send completed) ch.0/ch.1 Extended serial I/O UART (Reception completed) ch.0/ch.1 Time-base timer/Watch timer Flash memory status Delay interrupt output module x x x x x x x x x EI2OS DMAC support x x x x x x x x x x x x x 0, 1 2 to 6* x x x x x x x x x x 14 x 7 x 8 x x x x x 11 x 10 15 13 9 12 x x x
2
Interrupt vector Number*1 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 09H 0AH 0BH
Interrupt control register Priority Address ICR Address High
08H FFFFDCH FFFFD8H FFFFD4H FFFFD0H
0CH FFFFCCH 0DH FFFFC8H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH
1CH FFFF8CH
Low
(Continued) 31
MB90330A Series
(Continued) : Available, EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. With a stop request). : Available (The interrupt request flag is cleared by the interrupt clear signal.) : Available when any interrupt source sharing ICR is not used. x : Unavailable *1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : ch.2 and 3 can also be used during Mini-HOST operation. Notes : * If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. * The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). * If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the DMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to "0" in the appropriate resource, and take measures by software polling. * Content of USB interruption factor USB interrupt factor USB function 1 USB function 2 USB function 3 USB function 4 USB Mini-HOST1 USB Mini-HOST2 End Point1-5 * SUSP SOF BRST WKUP CONF SPK DIRQ CNNIRQ URIRQ RWKIRQ SOFIRQ CMPIRQ
Details End Point0-IN End Point0-OUT
* : Endpoints 1 and 2 can also be used during Mini-HOST operation.
32
MB90330A Series
PERIPHERAL RESOURCES
1. I/O port
The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90330A series model is provided with 12 ports (94 inputs) . The ports function as input/output pins for peripheral functions also. The port data register (PDR) can be used to send output data to the I/O pin and to receive the signal input to the I/O port. The port direction register (DDR) can be used to set the I/O direction of the I/O pin in bit units. The following table lists the I/O ports and the peripheral functions with which they share pins. Port Pin Name Port 0 Port 1 Port 2 Port 3 P00 to P07 P10 to P17 P20 to P23 P24 to P27 P30 to P33 P34 to P37 P40, P41 Port 4 Port 5 P42 to P47 P50 to P57 P60, P61 Port 6 P62 to P64 P65 P66, P67 Port 7 Port 8 Port 9 P70 to P77 P80 to P87 P90 to P95 P96 Port A PA0 to PA3 PA4 to PA7 PB0 to PB3 Port B PB4 PB5, PB6 Pin Name (Peripheral) PPG0 to PPG3 TIN1, TOT1, TIN2, TOT2 TIN0, TOT0 SIN0, SOT0, SCK0, SIN1, SOT1, SCK1 INT0, INT1 INT2 to INT4, SIN, SOT, SCK INT5, PWC INT6, INT7, SCL0, SDA0 AN0 to AN7 AN8 to AN15 SIN2, SOT2, SCK2, SIN3, SOT3, SCK3 ADTG, FRCK IN0 to IN3 OUT0 to OUT3 SCL1, SDA1, SCL2, SDA2 PPG4, PPG5 PPG timer 2 Peripheral Function that Shares Pin (External bus) (External bus) (External bus) 8/16-bit PPG timer 0, 1 (External bus) 16-bit Reload timer 1, 2 (External bus) (External bus) 16-bit Reload timer 0 (External bus) UART0, UART1 (External bus) (External bus) External interrupt External interrupt, Serial I/O External interrupt, PWC External interrupt, I2C 0 8/10-bit A/D converter 8/10-bit A/D converter UART2, 3 8/10-bit A/D converter, Free-run timer Input capture 0, 1, 2, 3 Output compare 0, 1, 2, 3 I2C 1, 2
Note : These pins also serve as the analog input pins for ports 7 and 8. To use them as general-purpose ports, be sure to set the corresponding bits in the analog input enable register (ADER) to 0B. The ADER is initialized to FFH at a reset.
33
MB90330A Series
* Register list (port data register) PDR0 bit
7 P07 15 P17 7 P27 15 P37 7 P47 15 P57 7 P67 15 P77 7 P87 15 7 PA7 7 6 P06 14 P16 6 P26 14 P36 6 P46 14 P56 6 P66 14 P76 6 P86 14 P96 6 PA6 6 PB6 5 P05 13 P15 5 P25 13 P35 5 P45 13 P55 5 P65 13 P75 5 P85 13 P95 5 PA5 5 PB5 4 P04 12 P14 4 P24 12 P34 4 P44 12 P54 4 P64 12 P74 4 P84 12 P94 4 PA4 4 PB4 3 P03 11 P13 3 P23 11 P33 3 P43 11 P53 3 P63 11 P73 3 P83 11 P93 3 PA3 3 PB3 2 P02 10 P12 2 P22 10 P32 2 P42 10 P52 2 P62 10 P72 2 P82 10 P92 2 PA2 2 PB2 1 P01 9 P11 1 P21 9 P31 1 P41 9 P51 1 P61 9 P71 1 P81 9 P91 1 PA1 1 PB1 0 P00 8 P10 0 P20 8 P30 0 P40 8 P50 0 P60 8 P70 0 P80 8 P90 0 PA0 0 PB0
Initial Value XXXXXXXXB
Access R/W*
Address : 000000H PDR1 bit
Address : 000001H PDR2 bit
XXXXXXXXB
R/W*
Address : 000002H PDR3 bit
XXXXXXXXB
R/W*
Address : 000003H PDR4 bit
XXXXXXXXB
R/W*
Address : 000004H PDR5 bit
XXXXXXXXB
R/W*
Address : 000005H PDR6 bit
XXXXXXXXB
R/W*
Address : 000006H PDR7 bit
XXXXXXXXB
R/W*
Address : 000007H PDR8 bit
XXXXXXXXB
R/W*
Address : 000008H PDR9 bit
XXXXXXXXB
R/W*
Address : 000009H PDRA bit
- XXXXXXXB
R/W*
Address : 00000AH PDRB bit
XXXXXXXXB
R/W*
Address : 00000CH
- XXXXXXXB
R/W*
* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows : * Input mode Read : The level at the relevant pin is read. Write : Data is written to the output latch. * Output mode Read : The data register latch value is read. Write : Data is output to the relevant pin.
34
MB90330A Series
* Register list (port direction register) DDR0 bit
7 D07 15 D17 7 D27 15 D37 7 D47 15 D57 7 D67 15 D77 7 D87 15 7 DA7 15 6 D06 14 D16 6 D26 14 D36 6 D46 14 D56 6 D66 14 D76 6 D86 14 D96 6 DA6 14 DB6 5 D05 13 D15 5 D25 13 D35 5 D45 13 D55 5 D65 13 D75 5 D85 13 D95 5 DA5 13 DB5 4 D04 12 D14 4 D24 12 D34 4 D44 12 D54 4 D64 12 D74 4 D84 12 D94 4 DA4 12 DB4 3 D03 11 D13 3 D23 11 D33 3 D43 11 D53 3 D63 11 D73 3 D83 11 D93 3 DA3 11 DB3 2 D02 10 D12 2 D22 10 D32 2 D42 10 D52 2 D62 10 D72 2 D82 10 D92 2 DA2 10 DB2 1 D01 9 D11 1 D21 9 D31 1 D41 9 D51 1 D61 9 D71 1 D81 9 D91 1 DA1 9 DB1 0 D00 8 D10 0 D20 8 D30 0 D40 8 D50 0 D60 8 D70 0 D80 8 D90 0 DA0 8 DB0
Initial Value Access 00000000B R/W
Address : 000010H DDR1 bit
Address : 000011H DDR2 bit
00000000B
R/W
Address : 000012H DDR3 bit
00000000B
R/W
Address : 000013H DDR4 bit
00000000B
R/W
Address : 000014H DDR5 bit
00000000B
R/W
Address : 000015H DDR6 bit
00000000B
R/W
Address : 000016H DDR7 bit
00000000B
R/W
Address : 000017H DDR8 bit
00000000B
R/W
Address : 000018H DDR9 bit
00000000B
R/W
Address : 000019H DDRA bit
-0000000B
R/W
Address : 00001AH DDRB bit
00000000B
R/W
Address : 00000DH
-0000000B
R/W
* When each pin is serving as a port, the corresponding pin is controlled as follows : 0 : Input mode 1 : Output mode This bit becomes 0 after a reset. Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to current input values of the pins. When switching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output. 35
MB90330A Series
* Register list (Analog input enable register) ADER0 ADER1 bit bit
15 14 13 12 ADE12 11 ADE11 10 ADE10 9 ADE9 8 ADE8 ADE15 ADE14 ADE13 7 ADE7 6 ADE6 5 ADE5 4 ADE4 3 ADE3 2 ADE2 1 ADE1 0 ADE0
Initial Value Access 11111111B R/W
Address : 00001EH
Address : 00001FH
11111111B
R/W
This register controls the port 7, 8 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. This bit becomes 1 after a reset. * Register list (Port pull-up resistance register) RDR0 bit
7 RD07 15 RD17 6 RD06 14 RD16 5 RD05 13 RD15 4 RD04 12 RD14 3 RD03 11 RD13 2 RD02 10 RD12 1 RD01 9 RD11 0 RD00 8 RD10
Initial Value Access 00000000B R/W
Address : 00001CH RDR1 bit
Address : 00001DH
00000000B
R/W
Controls the pull-up resistor in input mode. 0 : Without pull-up resistor in input mode. 1 : With pull-up resistor in input mode. Meaningless in output mode. (Without pull-up resistor)/The input/output mode is decided by the setting of the port direction register (DDR). Without pull-up resistor is used in stop mode (SPL = 1). (High-Z) This function is disabled when the external bus is used. Do not attempt to write to this register. * Register list (Output pin register) ODR4 bit
7 OD47 6 OD46 5 OD45 4 OD44 3 OD43 2 OD42 1 OD41 0 OD40
Initial Value Access 00000000B R/W
Address : 00001BH
Controls open-drain in output mode. 0 : Serves as a standard output port in output mode. 1 : Serves as an open-drain output port in output mode. Meaningless in input mode (output High-Z)./The input/output mode is decided by the setting of the port direction register (DDR). This function is disabled when the external bus is used. Do not attempt to write to this register.
36
MB90330A Series
* Block diagram of port 0 pin and port 1 pin
Pull-up resistor setting register (RDRx)
Internal pull-up resistor
Internal data bus
PDRx read Port data register (PDRx)
Port direction register (DDRx)
I/O decision circuit
Input buffer Output buffer Port pin
PDRx write
Standby control (LPMCR : SPL = "1")
* Block diagram of port 2 pin, port 3 pin, port 4 pin, port 5 pin, port 6 pin, port 9 pin, port A pin and port B pin
Resource input
Internal data bus
PDRx read Port data register (PDRx)
Port direction register (DDRx) Resource output control signal Resource output
I/O decision circuit
Input buffer Output buffer Port pin
PDRx write
Standby control (LPMCR : SPL = "1")
37
MB90330A Series
* Block diagram of port 7 pin and port 8 pin
Analog input enable register (ADER) Internal data bus
A/D converter analog input signal
Input buffer Output buffer Port pin
PDRx read
Port data register (PDRx) Port direction register (DDRx)
I/O decision circuit
PDRx write
Standby control (LPMCR : SPL = "1")
Notes : * When using as an input port, set "0" in the corresponding bit of the port-7 and port-8 direction register (DDR7 and DDR8) and "0" in the related bit of the analog input enable register (ADER). * When using as an analog input pin, set "0" in the corresponding bit of the port-7 and port-8 direction register (DDR7 and DDR8) and "1" in the related bit of the analog input enable register (ADER).
38
MB90330A Series
2. Time-base timer
The time-base timer is an 18-bit free-run counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock HCLK). Four different time intervals can be selected, for each of which an interrupt request can be generated. Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer. * Interval time of time-base timer Internal count clock cycle 2 /HCLK (Approx. 0.68 ms) 2/HCLK (0.33 s) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : * HCLK : Oscillation clock frequency * The parenthesized values assume an oscillator clock frequency of 6 MHz. * Clock cycles supplied from time-base timer Where to supply clock 213/HCLK (Approx. 1.36 ms) Main clock oscillation stabilization wait 215/HCLK (Approx. 5.46 ms) 217/HCLK (Approx. 21.84 ms) 212/HCLK (Approx. 0.68 ms) Watch dog timer 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : * HCLK : Oscillation clock frequency * The parenthesized values assume an oscillator clock frequency of 6 MHz. * Register list Time-base timer control register (TBTC) bit 15 14 Address : 0000A9H RESV
( R/W ) ()
12
Interval time
Clock cycle
13 ()
12 TBIE ( R/W )
11 TBOF ( R/W )
10 TBR (W)
9 TBC1 ( R/W )
8 TBC0 ( R/W )
Initial Value 1 - - 00100B
39
MB90330A Series
* Block Diagram
To PPG timer
Time-base timer counter
To watchdog timer
Dividing HCLK by 2
x 21 x 22
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF
Power-on reset Stop mode start Hold state start CKSCR : MCS = 10*1 CKSCR : SCS = 01*2
Counter clear control circuit
To clock controller oscillation stabilizing wait time selector
Interval timer selector
TBOF set
TBOF clear
Time-base timer control register (TBTC) RESV Time-base timer interrupt signal
TBIE TBOF TBR TBC1 TBC0
- OF HCLK *1 *2
: Unused : Overflow : Oscillation clock : Switching the machine clock from main clock or sub clock to PLL clock : Switching the machine clock from sub clock to main clock
Actual interrupt request number of time-base timer is as follows : Interrupt request number : #40 (28H)
40
MB90330A Series
3. Watchdog timer
The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time after start. * Interval time of watchdog timer HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 kHz) Min Approx. 2.39 ms Approx. 9.56 ms Approx. 38.23 ms Approx. 305.83 ms Approx. 0.448 s Approx. 3.584 s Approx. 7.168 s Approx. 14.336 s Max Approx. 3.07 ms Approx. 12.29 ms Approx. 49.15 ms Approx. 393.22 ms Approx. 0.576 s Approx. 4.608 s Approx. 9.216 s Approx. 18.432 s Clock cycle (214 211) /HCLK (216 213) /HCLK (218 215) /HCLK (221 218) /HCLK (212 29) /SCLK (215 212) /SCLK (216 213) /SCLK (217 214) /SCLK
Notes : * The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. * The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or watch timer. * Interval time of watchdog timer is longer than the set time during the following conditions. - When clearing the timebase timer during operation on oscillation (HCLK) - When clearing the watch timer during operation on sub clock (SCLK) * Events that stop the watchdog timer * Stop due to a power-on reset * Watchdog reset * Clear factor of watchdog timer * External reset input by RST pin * Writing "0" to the software reset bit * Writing "0" to the watchdog timer control bit (second and subsequent times) * Transition to sleep mode (clearing the watchdog timer to suspend counting) * Transition to time-base timer mode (clearing the watchdog timer to suspend counting) * Transition to stop mode (clearing the watchdog timer to suspend counting)
41
MB90330A Series
* Register list Watchdog timer control register (WDTC) bit 7 6 5 Address : 0000A8H PONR WRST
(R) () (R)
4 ERST (R)
3 SRST (R)
2 WTE (W)
1 WT1 (W)
0 WT0 (W)
Initial Value X-XXX111B
* Block Diagram Watchdog timer control register (WDTC)
PONR WRST ERST SRST WTE WT1 WT0
WDCS bit of WTC
Watch mode start Time-base timer mode start Sleep mode start Hold state start
2
SCM bit of CKSCR
Watchdog timer
Counter clear control circuit Count clock selector
CLR
CLR and start 2-bit counter
CLR
Stop mode start
Watchdog timer reset generation circuit
4
To internal reset generation circuit
Clear Main clock (dividing HCLK by 2)
x 21 x 22
4
(Time-base timer counter)
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
SCLK
x 21 x 22
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
HCLK: Oscillation clock SCLK: Sub clock
42
MB90330A Series
4. Watch timer
The watch timer is a 15-bit timer using the sub clock. It can generate interval interrupts. It can also be used as a clock source for the watchdog timer. * Register list Watch timer control register (WTC) bit 7 6 Address : 0000AAH WDCS SCE
( R/W ) (R)
5 WTIE ( R/W )
4 WTOF
3 WTR
2 WTC2 ( R/W )
1 WTC1 ( R/W )
0 WTC0 ( R/W )
Initial Value 10001000B
( R/W ) ( R/W )
* Block Diagram Watch timer control register (WTC)
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear
28 29
10 Watch counter 2
Sub clock
211 212 213 210 213 214 215 214
Interval selector
Interrupt generation circuit
Watch timer interrupt
To watchdog timer
43
MB90330A Series
5. 16-bit reload timer
The 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register setting + 1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. * Register list * TMCSR (Timer control status register 0 to 2) Timer control status register (upper) (TMCSR0 to TMCSR2) bit Address : 000063H 000067H 00006BH
15 () 14 () 13 () 12 () 11 CSL1 ( R/W ) 10 CSL0 ( R/W ) 9 MOD2 ( R/W ) 8 MOD1 ( R/W )
Initial Value XXXX0000B
Timer control status register (lower) (TMCSR0 to TMCSR2)
7 6 5 4 3 2 1 0 bit Address : 000062H MOD0 OUTE OUTL RELD INTE UF CNTE TRG 000066H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00006AH
Initial Value 00000000B
* 16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper) bit 15 14 13 12 11 10 9 8 Address : 000065H D15 D14 D13 D12 D11 D10 D09 D08 000069H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00006DH TMR0 to TMR2/TMRLR0 to TMRLR2 (lower) bit 7 6 5 4 3 Address : 000064H D07 D06 D05 D04 D03 000068H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00006CH
2 D02 1 D01 0 D00 ( R/W )
Initial Value XXXXXXXXB
Initial Value XXXXXXXXB
( R/W ) ( R/W )
44
MB90330A Series
* Block diagram Internal data bus
TMRLR01 TMRLR12 TMRLR23
16-bit reload register
TMR01 TMR12 TMR23
Reload signal
5
Reload control circuit
16-bit timer register Count clock generation circuit Machine clock
Prescaler
UF
CLK
3
Gate input
Valid clock decision circuit
Wait signal
Clear Trigger
Input control circuit
Internal clock
CLK
Output control circuit
Output signal generation circuit
Pin
TIN01 TIN12 TIN23
Clock selector External clock Select signal
Pin
EN TOT01 TOT12 TOT23
Operating control circuit
3
2
Select function

CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
UF CNTE TRG
Timer control status register (TMCSR0 to TMCSR2) Interrupt request output #23 (17H) *1, *4 #26 (1AH) *2, *4 #28 (1CH) *3, *4
*1 : ch.0 *2 : ch.1 *3 : ch.2 *4 : Interrupt number *5 : Underflow
45
MB90330A Series
6. Multi function timer
The multi-function timer enables the following based on the 16-bit free-run timer. * Output of independent waveform * Measurement of input pulse width * Measurement of external clock cycle * Configuration of a multi-functional timer 16-bit free-run timer 16-bit Output Compare 16-bit Input Capture 8/16-bit PPG timer 16-bit PWC timer 1 channel 4 channels 4 channels 8-bit x 6 channels (16-bit x 3 channels) 1 channel
* 16-bit free-run timer : 1 channel The 16-bit free-run timer consists of a 16-bit up counter (timer data register (TCDT)), compare clear register (CPCLR), timer control status register (TCCS), and prescaler. The counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input capture units. * The count clock can be set, selected from among the following eight types. 1/, 2/, 4/, 8/, 16/, 32/, 64/, 128/ : Machine clock frequency * During the following conditions, the interrupt should be output. - The counter value of 16-bit free run timer will be overflowed. - The counter value of 16-bit free run timer will be cleared after the counter value of 16-bit free run timer = the compare clear register value (CPCLR) (TCCS : ICRE = "1", MODE = "1") * The counter value of 16-bit free run timer should be cleared to "0000H" during the following conditions. * Reset * When setting the clear bit (SCLR) of timer control status register (TCCS) to "1" * When the counter value of the 16-bit free run timer = the compare clear register value (CPCLR) (TCCS : MODE = "1") * When setting "0000H" to the timer data register (TCDT) * Output compare : 4 channels The output compare unit consists of compare registers (OCCP0 to OCCP3), compare control registers (OCS0 to OCS3), and a compare output latch. The output compare unit can invert the output level and output an interrupt when a compare register (OCCP0 to OCCP3) value matches the counter value of the 16-bit free-run timer. * Output compare registers can operate as 4 independent channels. The output compare registers (OCCP0 to OCCP3) of each channel have interrupt request flags of their respective output pins. * Pin output can be inverted by using 2 channels of output compare registers (OCCP0 to OCCP3). * If the counter value of 16-bit free run timer = the output compare register (OCCP0 to OCCP3) (OCS0, OCS2 : ICP0 = "1", ICP1 = "1"), the interrupt request should be generated. (OCS0, OCS2 : ICE0 = "1", ICE1 = "1") * The initial value for pin output of each channel can be set. * Input capture : 4 channels The input capture unit consists of the input capture data registers (IPCP0 to IPCP3) corresponding to external input pins (IN0 to IN3) and input capture control registers (ICS01, ICS23). The input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data register (IPCP0 to IPCP3) to generated an interrupt request upon detection of the effective edge of the signal input through the external input.
46
MB90330A Series
* The input capture unit in each channel can operate independently. * The effective edge of the external signal can be selected (rising edge, falling edge, both edges). * An interrupt request can be generated upon detection of the selected effective edge of the external signal.(ICS01, ICS2 : ICE0 = "1", ICE1 = "1", ICE2 = "1", ICE3 = "1"). * Register list (16-bit free-run timer) Compare clear register (CPCLR) bit 15 14 Address : 00008BH CL15 CL14
( R/W ) ( R/W )
13 CL13 ( R/W )
12 CL12 ( R/W )
11 CL11 ( R/W )
10 CL10
9 CL09
8 CL08 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
bit Address : 00008AH
7 CL07 ( R/W )
6 CL06
5 CL05
4 CL04 ( R/W )
3 CL03 ( R/W )
2 CL02
1 CL01
0 CL00 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
( R/W ) ( R/W )
Timer data register (TCDT) bit 15 Address : 000087H T15
( R/W )
14 T14
13 T13
12 T12 ( R/W )
11 T11 ( R/W )
10 T10
9 T09
8 T08 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
( R/W ) ( R/W )
bit Address : 000086H
7 T07 ( R/W )
6 T06
5 T05
4 T04 ( R/W )
3 T03 ( R/W )
2 T02
1 T01
0 T00 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
( R/W ) ( R/W )
Timer control/status register (TCCS) bit 15 14 Address : 000089H ECKE
( R/W )
13
12 MSI2 ( R/W )
11 MSI1 ( R/W )
10 MSI0
9 ICLR
8 ICRE ( R/W )
Initial Value 0--00000B
( R/W ) ( R/W )
( R/W ) ( R/W )
bit Address : 000088H
7 IVF ( R/W )
6 IVFE
5 STOP
4 MODE
3 SCLR ( R/W )
2 CLK2
1 CLK1
0 CLK0 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W ) ( R/W )
( R/W ) ( R/W )
47
MB90330A Series
* Register list (output compare) Compare register (OCCP0 to OCCP3) bit 15 14 13 12 11 10 9 8 Address : 007919H C15 C14 C13 C12 C11 C10 C09 C08 00791BH 00791DH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00791FH bit 7 6 5 4 3 2 1 0 Address : 007918H C07 C06 C05 C04 C03 C02 C01 C00 00791AH 00791CH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00791EH Control register (OCS1/OCS3) bit 15 Address : 000055H 000057H Initial Value XXXXXXXXB
Initial Value XXXXXXXXB
14 ()
13 ()
12 CMOD ( R/W )
11 OTE1 ( R/W )
10 OTE0
9 OTD1
8 OTD0 ( R/W )
Initial Value ---00000B
()
( R/W ) ( R/W )
Control register (OCS0/OCS2) bit 7 Address : 000054H ICP1 000056H
6 ICP0
5 ICE1
4 ICE0 ( R/W )
3 ()
2 ()
1 CST1 ( R/W )
0 CST0 ( R/W )
Initial Value 0000--00B
( R/W )
( R/W ) ( R/W )
48
MB90330A Series
* Register list (input capture) Input capture data register (IPCP0 to IPCP3) bit 15 14 13 Address : 007911H CP15 CP14 CP13 007913H (R) (R) (R) 007915H 007917H bit Address : 007910H 007912H 007914H 007916H Initial Value XXXXXXXXB
12 CP12 (R)
11 CP11 (R)
10 CP10 (R)
9 CP09 (R)
8 CP08 (R)
7 CP07 (R)
6 CP06 (R)
5 CP05 (R)
4 CP04 (R)
3 CP03 (R)
2 CP02 (R)
1 CP01 (R)
0 CP00 (R)
Initial Value XXXXXXXXB
Input capture control status register (ICS23) bit 15 14 13 Address : 000053H ICP3 ICP2 ICE3
( R/W ) ( R/W ) ( R/W )
12 ICE2 ( R/W )
11 EG31 ( R/W )
10 EG30
9 EG21
8 EG20 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
Input capture control status register (ICS01) bit 7 6 5 Address : 000052H ICP1 ICP0 ICE1
( R/W ) ( R/W ) ( R/W )
4 ICE0 ( R/W )
3 EG11 ( R/W )
2 EG10
1 EG01
0 EG00 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
49
MB90330A Series
* Block diagram of the 16-bit free-run timer, input capture units, and output compare units
To interrupt #36 (24H)*
8 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0
3
Divider Clock
16-bit free-run timer
16
16-bit compare clear register
16
Compare circuit
To interrupt #36 (24H)*
ICLR T Q ICRE
Compare register 0/2 Compare circuit Internal data bus
16
MSI2 to MSI0
OTE0
OUT0/OUT2
Compare register 1/3 Compare circuit
CMOD T Q OTE1 OUT1/OUT3
4 ICP1 ICP0 IOE1 IOE0
To interrupt #29 (1DH)*
#31 (1FH)* Capture data register 0/2
4
Edge detection
IN0/IN2
EG11 EG31
EG10 EG30
EG01 EG21
EG00 EG20
Capture data register 1/3
4 ICP1 ICP3 ICP0 ICP2
Edge detection
IN1/IN3
ICE1 ICE3
ICE0 ICE2
To interrupt #25 (19H)* #27 (1BH)*
* : Interrupt number : Machine clock frequency
50
MB90330A Series
* 8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels) 8/16-bit PPG timer consists of an 8-bit down counter (PCNT), PPG operation mode control register (PPGC0 to PPGC5), PPG output control register (PPG01, PPG23, PPG45) and PPG reload register (PRLL0 to PRLL5, PRLH0 to PRLH5). When used as an 8-/16-bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an arbitrary duty ratio at an arbitrary frequency. * 8-bit PPG mode Each channel operates as an independent 8-bit PPG. * 8-bit prescaler + 8-bit PPG mode Operates as an arbitrary-cycle 8-bit PPG with PPG0 (PPG2, PPG4) operating as an 8-bit prescaler and PPG1 (PPG3, PPG5) counted by the borrow output of PPG0 (PPG2, PPG4). * 16-bit PPG mode Operates as a 16-bit PPG with PPG0 (PPG2, PPG4) and PPG1 (PPG3, PPG5) connected. * PPG operation The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of pulse waveform) at an arbitrary frequency. This can also be used as a D/A converter by an external circuit.
51
MB90330A Series
* Register list PPG operation mode control register (PPGC1/PPGC3/PPGC5) bit 15 14 Address : 000047H PEN1 000049H 00004BH ( R/W ) ( ) (PPGC0/PPGC2/PPGC4) bit 7 Address : 000046H PEN0 000048H 00004AH ( R/W )
13 PE10 ( R/W )
12 PIE1 ( R/W )
11 PUF1 ( R/W )
10 MD1
9 MD0
8
Reserved
Initial Value 0X000001B
( R/W ) ( R/W )
( R/W )
6 ()
5 PE00 ( R/W )
4 PIE0 ( R/W )
3 PUF0 ( R/W )
2 ()
1 ()
0
Reserved
Initial Value 0X000XX1B
( R/W )
PPG output control register (PPG01/PPG23/PPG45) bit 7 6 5 4 3 2 1 0 Address : 00004CH PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved 00004EH 000050H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) PPG reload register (PRLH0 to PRLH5) bit 15 14 13 12 11 10 9 8 Address : 007901H D15 D14 D13 D12 D11 D10 D09 D08 007903H 007905H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 007907H 007909H 00790BH (PRLL0 to PRLL5) bit 7 6 5 4 3 2 1 0 Address : 007900H D07 D06 D05 D04 D03 D02 D01 D00 007902H 007904H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 007906H 007908H 00790AH
Initial Value 000000XXB
Initial Value XXXXXXXXB
Initial Value XXXXXXXXB
52
MB90330A Series
* 8/16-bit PPG ch.0/ch.2/ch.4 block diagram
Peripheral clock dividing by 16 Peripheral clock dividing by 8 Peripheral clock dividing by 4 Peripheral clock dividing by 2 Peripheral clock
PPG0/PPG2/PPG4 output enable
PPG0/PPG2/PPG4 A/D converter
PPG0/PPG2/PPG4 output latch
PEN0 PCNT (down counter) Count clock select "L"/"H" selector Dividing by 512 of timebase counter output main clock "L"/"H" select PRLL PRLBH S RQ
To interrupt #30 (1EH)* #32 (20H)* IRQ #34 (22H)* ch.1/ch.3/ch.5 borrow
PUF0
PIE0
PPGC0 (operating mode control) PRLL "L" data bus "H" data bus
* : Interrupt number
53
MB90330A Series
* 8-bit PPG ch.1/ch.3/ch.5 block diagram
Peripheral clock dividing by 16 Peripheral clock dividing by 8 Peripheral clock dividing by 4 Peripheral clock dividing by 2 Peripheral clock
PPG1/PPG3/PPG5 output enable
PPG1/PPG3/PPG5
PPG1/PPG3/PPG5 output latch
PEN1 PCNT (down counter) Count clock select "L"/"H" selector Dividing by 512 timebase counter output main clock "L"/"H" select PRLL PRLBH PPGC1 (operating mode control) PRLL "L" data bus "H" data bus S RQ
IRQ
To interrupt #30 (1EH)* #32 (20H)* #34 (22H)*
PUF1
PIE1
* : Interrupt number
54
MB90330A Series
* PWC timer The PWC timer is a 16-bit multi-function up-count timer capable of measuring the input signal pulse width. * Register list PWC control status register (PWCSR) bit 15 14 Address : 00005DH STRT STOP
( R/W ) ( R/W )
13 EDIR (R)
12 EDIE ( R/W )
11 OVIR ( R/W )
10 OVIE ( R/W )
9 ERR (R)
8
Reserved
( R/W )
Initial Value 0000000XB
bit Address : 00005CH
7 CKS1 ( R/W )
6 CKS0 ( R/W )
5 PIS1 ( R/W )
4 PIS0 ( R/W )
3 S/C ( R/W )
2 MOD2
1 MOD1
0 MOD0 ( R/W )
( R/W ) ( R/W )
Initial Value 00000000B
PWC data buffer register (PWCR) bit 15 14 Address : 00005FH D15 D14
( R/W ) ( R/W )
13 D13 ( R/W )
12 D12 ( R/W )
11 D11 ( R/W )
10 D10
9 D9
8 D8 ( R/W )
( R/W ) ( R/W )
Initial Value 00000000B
bit Address : 00005EH
7 D7 ( R/W )
6 D6 ( R/W )
5 D5 ( R/W )
4 D4 ( R/W )
3 D3
2 D2
1 D1 ( R/W )
0 D0 ( R/W )
( R/W ) ( R/W )
Initial Value 00000000B
PWC ratio of dividing frequency control register (DIVR) bit 7 6 5 4 Address : 000060H
() () () ()
3 ()
2 ()
1 DIV1 ( R/W )
0 DIV0 ( R/W )
Initial Value ------00B
55
MB90330A Series
* Block Diagram
PWCR read
Error detection
ERR PWCR
16
Reload Data transfer Overflow 16-bit up count timer F2MC-16 bus Timer clear
16
Internal clock (machine clock/4)
Clock
22 2 CKS1/CKS0
3
Clock divider Divider clear
Control circuit Flag set etc...
Control bit output Start edge selection Measurement starting edge Measurement termination edge End edge selection
Count enable
Edge detection
PIS0/PIS1
Divider ON/OFF
Input waveform comparator
PWC
Measurement termination interrupt request
8-bit divider
Overflow interrupt request
15 PWCSR 2
ERR
CKS0/CKS1
Divide ratio select
DIVR
56
MB90330A Series
7. UART
UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. It supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). An interrupt can be generated upon completion of reception, detection of a reception error, or completion of transmission. EI2OS is supported. * UART functions UART, or a generic serial data communication interface that sends and receives serial data to and from other CPU and peripherals, has the functions listed in following. Function Data buffer Transmission mode Full-duplex double-buffered * Clock synchronous (without start/stop bit) * Clock asynchronous (start-stop synchronous) * Special-purpose baud-rate generator It is optional from 8 kinds. * Baud rate by external clock (SCK0/SCK1/SCK2/SCK3 terminal input) * 8-bit or 7-bit (in the asynchronous normal mode only) * 1-bit to 8-bit (synchronous mode only) Non Return to Zero (NRZ) system * Framing error * Overrun error * Parity error (Not supported in operation mode 1) * Receive interrupt (reception completed, reception error detected) * Transmission interrupt (transmission completed) * Both the transmission and reception support EI2OS. Capable of 1 (master) to many (slaves) communication (available just as master)
Baud rate
Data length Signal system Reception error detection
Interrupt request Master/slave type communication function (multi processor mode)
Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added. * UART operation modes Operation mode 0 1 2 Normal mode Multi processor mode Normal mode Data length Without parity 8-bit + 1*1 1 to 8-bit With parity 7-bit or 8-bit Synchronization Asynchronous Asynchronous Synchronous Stop bit length 1-bit or 2-bit *2 No
: Setting disabled *1 : + 1 is an address/data setting bit (A/D) which is used for communication control. *2 : Only one bit can be detected as a stop bit at reception.
57
MB90330A Series
* Register list Serial mode register (SMR0 to SMR3) bit 7 6 5 4 3 2 1 0 Address : 000020H M2L0 MD1 MD0 SCKL M2L2 M2L1 SCKE SOE 000026H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00002CH 000032H Serial control register (SCR0 to SCR3) bit 15 14 13 12 11 Address : 000021H PEN P SBL CL A/D 000027H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00002DH 000033H Initial Value 00100000B
10 REC (W)
9 RXE ( R/W )
8 TXE ( R/W )
Initial Value 00000100B
Serial input/output data register (SIDR0 to SIDR3 / SODR0 to SODR3) bit 7 6 5 4 3 2 1 0 Address : 000022H D7 D6 D5 D4 D3 D2 D1 D0 000028H ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 00002EH 000034H Serial status register (SSR0 to SSR3) bit 15 14 Address : 000023H PE ORE 000029H (R) (R) 00002FH 000035H
Initial Value XXXXXXXXB
13 FRE (R)
12 RDRF (R)
11 TDRE (R)
10 BDS ( R/W )
9 RIE ( R/W )
8 TIE ( R/W )
Initial Value 00001000B
UART prescaler reload register (UTRLR0 to UTRLR3) bit 7 6 5 4 3 2 1 0 Address : 000024H D7 D6 D5 D4 D3 D2 D1 D0 00002AH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 000030H 000036H UART prescaler control register (UTCR0 to UTCR3) bit 15 14 13 12 11 Address : 000025H Reserved MD SRST CKS 00002BH ( R/W ) ( R/W ) ( R/W ) ( R/W ) () 000031H 000037H
Initial Value 00000000B
10 D10 ( R/W )
9 D9 ( R/W )
8 D8 ( R/W )
Initial Value 0000-000B
58
MB90330A Series
* Block Diagram Control bus
Special-purpose baud-rate generator (UART prescaler control register UTCR0 to UTCR3) (UART prescaler reload UTRLR0 to UTRLR3) Reception interrupt signal #39 (27H)* #35 (23H)* Send interrupt signal #37 (25H)* #33 (21H)*
Transmission clock Clock selector
Reception Reception control clock
circuit Start bit detection circuit Reception bit counter Reception parity counter
Transmission control circuit
Pin
Transmission start circuit Transmission bit counter Transmission parity counter
SCK0 to SCK3
Pin
SOT0 to SOT3
Pin
SIN0 to SIN3
Shift register for reception
Shift register for transmission
SIDR0 to SIDR3
Receive status decision circuit
SODR0 to SODR3
Start transmission
Reception error occurrence signal for EI2OS * DMAC (to CPU)
Reception complete
Internal data bus
SMR0 to SMR3
MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE
SCR0 to SCR3
PEN P SBL CL A/D REC RXE TXE
SSR0 to SSR3
PE ORE FRE RDRF TDRE BDS RIE TIE
* : Interrupt number
59
MB90330A Series
8. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface in an 8-bit, single-channel, capable of clock synchronous data transfer. LSB-first or MSB-first transfer mode can be selected for data transfer. There are 2 serial I/O operation modes available: * Internal shift clock mode: Transfer data in synchronization with the internal clock. * External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK). By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be transferred by a CPU instruction. * Register list Serial mode control status register (SMCS) bit 15 14 13 Address : 000059H
SMD2 ( R/W ) SMD1 ( R/W ) 6 () SMD0
12 SIE
11 SIR ( R/W ) 3 MODE ( R/W )
10 BUSY (R) 2 BDS ( R/W )
9 STOP ( R/W ) 1 SOE ( R/W )
8 STRT ( R/W ) 0 SCOE ( R/W )
Initial Value 00000010B
( R/W ) ( R/W ) 5 () 4 ()
bit Address : 000058H
7 ()
Initial Value XXXX0000B
Serial data register (SDR) bit Address : 00005AH
7 D7
6 D6
5 D5 ( R/W )
4 D4 ( R/W )
3 D3 ( R/W )
2 D2
1 D1
0 D0 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
( R/W ) ( R/W )
Communication prescaler control register (SDCR) bit 15 14 13 12 MD Address : 00005BH
( R/W ) () () ()
11 DIV3 ( R/W )
10 DIV2
9 DIV1
8 DIV0 ( R/W )
Initial Value 0XXX0000B
( R/W ) ( R/W )
60
MB90330A Series
* Block Diagram
Internal data bus (MSB fast) D0 to D7
SIN
Initial value D7 to D0 (LSB fast) Transfer direction selection Read Write
SDR (serial data register)
SOT
SCK
Control circuit
Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
61
MB90330A Series
9. I2C Interface
The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C bus and has the following features. * Master/slave sending and receiving * Arbitration function * Clock synchronization function * Slave address and general call address detection function * Detecting transmitting direction function * Start condition repeated generation and detection function * Bus error detection function * Register list I2C bus status register (IBSR0 to IBSR2) bit Address : 000070H 000076H 00007CH
7 BB (R) 6 RSC (R) 5 AL (R) 4 LRB (R) 3 TRX (R) 2 AAS (R) 1 GCA (R) 0 FBT (R)
Initial Value 00000000B
I2C bus control register (IBCR0 to IBCR2) bit Address : 000071H 000077H 00007DH
15 BER ( R/W ) 14 BEIE ( R/W ) 13 SCC ( R/W ) 12 MSS 11 ACK 10 GCAA ( R/W ) 9 INTE ( R/W ) 8 INT ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
I2C bus clock control register (ICCR0 to ICCR2) bit Address : 000072H 000078H 00007EH
7 () 6 () 5 EN ( R/W ) 4 CS4 ( R/W ) 3 CS3 2 CS2 1 CS1 ( R/W ) 0 CS0 ( R/W )
Initial Value XX0XXXXXB
( R/W ) ( R/W )
I2C bus address register (IADR0 to IADR2) bit Address : 000073H 000079H 00007FH
15 () 14 A6 ( R/W ) 13 A5 ( R/W ) 12 A4 ( R/W ) 11 A3 10 A2 9 A1 ( R/W ) 8 A0 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
I2C bus data register (IDAR0 to IDAR2) bit Address : 000074H 00007AH 000080H
7 D7 ( R/W ) 6 D6 ( R/W ) 5 D5 ( R/W ) 4 D4 3 D3 2 D2 ( R/W ) 1 D1 ( R/W ) 0 D0 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
62
MB90330A Series
* Block Diagram
ICCRx EN
I2C enable Clock divide 1
5 6 7 8
Peripheral clock
ICCRx CS4 CS3 CS2 CS1 CS0
Clock selector 1 Clock divide 2
2 4 8 16 32 64 128 256 Sync
Generating shift clock
Clock selector 2
Shift clock edge change timing
IBSRx
F2MC-16 bus
BB RSC LRB TRX FBT AL
Bus busy Repeat start
Last Bit
Send/receive
Start stop condition detection Error
First Byte
Arbitration lost detection
IBCRx BER BEIE SCLx
Interrupt request
INTE INT IBCRx SCC MSS ACK GCAA
IRQ
SDAx
Start Master ACK enable
GC-ACK enable
End Start stop condition generation
IDAR IBSRx AAS GCA
Slave Global call Slave address compare
IADR
63
MB90330A Series
10. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol. * Feature of USB function * Correspond to USB Full Speed * Full speed (12 Mbps) is supported. * The device status is auto-answer. * Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16 * Toggle check by data synchronization bit * Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these 3 commands can be processed the same way as the class vendor commands). * The class vendor commands can be received as data and responded via firmware. * Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer) * 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0) * Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0) * Register list UDC control register (UDCC) bit Address : 0000D0H
7 RST 6 5 4 3 2 1 RFBK ( R/W )
9
0 PWC ( R/W )
8
RESUM HCON ( R/W )
13
USTP Reserved Reserved ( R/W )
12
Initial Value 10100000B
( R/W ) ( R/W )
()
11
()
10
bit Address : 0000D1H
15
14
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Initial Value 00000000B
()
()
()
()
()
()
()
()
EP0 control register (EP0C) bit Address : 0000D2H
7
Reserved
6 PKS0 ( R/W ) 14 ()
5 PKS0 ( R/W ) 13 ()
4 PKS0 ( R/W ) 12 ()
3 PKS0 ( R/W ) 11
2 PKS0 ( R/W ) 10
1 PKS0 ( R/W ) 9 STAL ( R/W )
0 PKS0 ( R/W ) 8
Reserved
Initial Value 01000000B
()
bit Address : 0000D3H
15 ()
Reserved Reserved
Initial Value XXXX0000B
()
()
()
EP1 control register (EP1C) bit Address : 0000D4H
7 PKS1 ( R/W ) 6 PKS1 ( R/W ) 14 TYPE ( R/W ) 5 PKS1 ( R/W ) 13 TYPE ( R/W ) 4 PKS1 ( R/W ) 12 DIR ( R/W ) 3 PKS1 ( R/W ) 11 DMAE ( R/W ) 2 PKS1 1 PKS1 0 PKS1 ( R/W ) 8 PKS1 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W ) 10 NULE ( R/W ) 9 STAL ( R/W )
bit Address : 0000D5H
15 EPEN ( R/W )
Initial Value 01100001B
(Continued) 64
MB90330A Series
EP2/3/4/5 control register (EP2C to EP5C) bit Address : 0000D6H 0000D8H 0000DAH 0000DCH bit Address : 0000D7H 0000D9H 0000DBH 0000DDH
7 6 5 4 3 2 1 0
Reserved PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5
Initial Value 01000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15 EPEN ( R/W )
14 TYPE ( R/W )
13 TYPE ( R/W )
12 DIR ( R/W )
11 DMAE ( R/W )
10 NULE ( R/W )
9 STAL ( R/W )
8
Reserved
Initial Value 01100000B
( R/W )
Time stamp register (TMSP) bit Address : 0000DEH
7 TMSP (R) 6 TMSP (R) 5 TMSP (R) 4 TMSP (R) 3 TMSP (R) 2 TMSP (R) 1 TMSP (R) 0 TMSP (R)
Initial Value 00000000B
bit Address : 0000DFH
15 ()
14 ()
13 ()
12 ()
11 ()
10 TMSP (R)
9 TMSP (R)
8 TMSP (R)
Initial Value XXXXX000B
UDC status register (UDCS) bit Address : 0000E0H
7 () 6 () 5 SUSP ( R/W ) 4 SOF ( R/W ) 3 BRST ( R/W ) 2 WKUP ( R/W ) 1 SETP ( R/W ) 0 CONF ( R/W )
Initial Value XX000000B
UDC Interrupt enable register (UDCIE) bit Address : 0000E1H
15 14 13 12 SOFIE ( R/W ) 11 10 9 8
Reserved Reserved SUSPIE
BRSTIE WKUPIE CONFN CONFIE ( R/W ) ( R/W ) (R) ( R/W )
Initial Value 00000000B
()
()
( R/W )
EP0I status register (EP0IS) bit Address : 0000E2H
7 () 6 () 5 () 4 () 3 () 2 () 1 () 0 ()
Initial Value XXXXXXXXB
bit Address : 0000E3H
15 BFINI ( R/W )
14 DRQIIE ( R/W )
13 ()
12 ()
11 ()
10 DRQI ( R/W )
9 ()
8 ()
Initial Value 10XXX1XXB
(Continued) 65
MB90330A Series
(Continued) EP0O status register (EP0OS) bit Address : 0000E4H
7
Reserved
6 SIZE (R)
5 SIZE (R)
4 SIZE (R)
3 SIZE (R)
2 SIZE (R)
1 SIZE (R)
0 SIZE (R)
Initial Value 0XXXXXXXB
()
bit Address : 0000E5H
15 BFINI ( R/W )
14
13
12 ()
11 ()
10 DRQO ( R/W )
9 SPK ( R/W )
8
Reserved
DRQOIE SPKIE ( R/W ) ( R/W )
Initial Value 100XX000B
()
EP1 status register (EP1S) bit Address : 0000E6H
7 SIZE (R) 6 SIZE (R) 5 SIZE (R) 4 SIZE (R) 3 SIZE (R) 2 SIZE (R) 1 SIZE (R) 0 SIZE (R)
Initial Value XXXXXXXXB
bit Address : 0000E7H
15 BFINI ( R/W )
14 DRQIE ( R/W )
13
12
11 BUSY (R)
10 DRQ ( R/W )
9 SPK ( R/W )
8 SIZE (R)
SPKIE Reserved ( R/W ) ()
Initial Value 1000000XB
EP2/3/4/5 status register (EP2S to EP5S) bit Address : 0000E8H 0000EAH 0000ECH 0000EEH
;
7
Reserved
6 SIZE (R)
5 SIZE (R)
4 SIZE (R)
3 SIZE (R)
2 SIZE (R)
1 SIZE (R)
0 SIZE (R)
Initial Value XXXXXXXXB
()
bit 15 14 13 Address : 0000E9H BFINI DRQIE SPKIE 0000EBH ( R/W ) ( R/W ) ( R/W ) 0000EDH 0000EFH EP0/1/2/3/4/5 data register (EP0DT to EP5DT) bit Address : 0000F0H 0000F2H 0000F4H 0000F6H 0000F8H 0000FAH bit Address : 0000F1H 0000F3H 0000F5H 0000F7H 0000F9H 0000FBH
7 BFDT ( R/W ) 6 BFDT ( R/W ) 5 BFDT ( R/W )
12
Reserved
11 BUSY (R)
10 DRQ ( R/W )
9 SPK ( R/W )
8
Reserved
Initial Value 10000000B
()
()
4 BFDT ( R/W )
3 BFDT ( R/W )
2 BFDT ( R/W )
1 BFDT ( R/W )
0 BFDT ( R/W )
Initial Value XXXXXXXXB
15 BFDT ( R/W )
14 BFDT ( R/W )
13 BFDT ( R/W )
12 BFDT ( R/W )
11 BFDT ( R/W )
10 BFDT
9 BFDT
8 BFDT ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
66
MB90330A Series
11. USB Mini-HOST
USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred to and from Device without PC intervention. * Feature of USB Mini-HOST * Automatic detection of Low Speed/Full Speed transfer * Low Speed/Full Speed transfer support * Automatic detection of connection and cutting device * Reset sending function support to USB-bus * Support of IN/OUT/SETUP/SOF token * In-token handshake packet automatic transmission (excluding STALL) * Out-token handshake packet automatic detection * Supports a maximum packet length of 256 bytes. * Error (CRC error/toggle error/time-out) various supports * Wake-Up function support * Differences between the USB HOST and USB Mini-HOST HOST Hub support Bulk transfer Transfer Control transfer Interrupt transfer ISO transfer Transfer speed PRE packet support SOF packet support CRC error Error Toggle error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection : Supported x : Not supported Low Speed Full Speed x x Mini-HOST x
67
MB90330A Series
* Register list Host control register 0 (HCNT0) bit Address : 0000C0H
7 6 5 4 3 DIRE ( R/W ) 2 SOFIRE ( R/W ) 1 URST ( R/W ) 0 HOST ( R/W )
RWKIRE URIRE CMPIRE CNNIRE ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
Host control register 1 (HCNT1) bit Address : 0000C1H
15 14 13 12 11 10 9 8
Reserved Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY
Initial Value 00000001B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
Host interruption register (HIRQ) bit Address : 0000C2H
7 6 5 4 3 2 1 DIRQ ( R/W ) 0 SOFIRQ ( R/W ) TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
Host error status register (HERR) bit Address : 0000C3H
15 14 13 TOUT ( R/W ) 12 CRC ( R/W ) 11 10 9 HS ( R/W ) 8 HS ( R/W )
LSTSOF RERR ( R/W ) ( R/W )
TGERR STUFF ( R/W ) ( R/W )
Initial Value 00000011B
Host state status register (HSTATE) bit Address : 0000C4H
7 () 6 () 5 4 3 2 1 0 ALIVE CLKSEL SOFBUSY SUSP ( R/W ) ( R/W ) ( R/W ) ( R/W ) TMODE CSTAT (R) (R)
Initial Value XX010010B
SOF interruption FRAME comparison register (HFCOMP) bit Address : 0000C5H
15
FRAME COMP
14
FRAME COMP
13
FRAME COMP
12
FRAME COMP
11
FRAME COMP
10
FRAME COMP
9
FRAME COMP
8
FRAME COMP
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
(Continued)
68
MB90330A Series
(Continued) Retry timer setting register (HRTIMER) bit Address : 0000C6H
7 6 5 4 3 2 1 0
RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
bit Address : 0000C7H
15
14
13
12
11
10
9
8
RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
bit Address : 0000C8H
7 ()
6 ()
5 ()
4 ()
3 ()
2 ()
1
0
RTIMER2 RTIMER2
Initial Value XXXXXX00B
( R/W )
( R/W )
Host address register (HADR) bit Address : 0000C9H
15 () 14 13 12 11 10 9 8
ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS
Initial Value X0000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
EOF setting register (HEOF) bit Address : 0000CAH
7 EOF0 ( R/W ) 6 EOF0 ( R/W ) 5 EOF0 ( R/W ) 4 EOF0 ( R/W ) 3 EOF0 ( R/W ) 2 EOF0 ( R/W ) 1 EOF0 ( R/W ) 0 EOF0 ( R/W )
Initial Value 00000000B
bit Address : 0000CBH
15 ()
14 ()
13 EOF1 ( R/W )
12 EOF1 ( R/W )
11 EOF1 ( R/W )
10 EOF1 ( R/W )
9 EOF1 ( R/W )
8 EOF1 ( R/W )
Initial Value XX000000B
FRAME setting register (HFRAME) bit Address : 0000CCH
7 6 5 4 3 2 1 0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
bit Address : 0000CDH
15 ()
14 ()
13 ()
12 ()
11 ()
10
9
8
FRAME1 FRAME1 FRAME1
Initial Value XXXXX000B
( R/W )
( R/W )
( R/W )
Host token end point register (HTOKEN) bit Address : 0000CEH
7 TGGL ( R/W ) 6 5 4 3 2 1 0 TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
69
MB90330A Series
12. 8/10-bit A/D converter
The A/D converter converts analog input voltages into digital values and has the following features. * RC sequential compare conversion method with sample and hold circuit * Selectable 8-bit resolution or 10-bit resolution * Analog input program-selectable from among 16 channels Single conversion mode : Convert 1 selected channel Scan conversion mode : Continuous plural channels (maximum 16 channels can be programmed) are converted. Continuous conversion mode : Repeatedly convert the specified channels. Stop conversion mode: Convert 1 channel then suspend conversion to remain on standby until the next activation (Simultaneous conversion start available). * An interrupt request to the CPU can be generated upon completion of A/D conversion. Suitable for continuous processing as this interrupt activates DMA to transfer the data resulting from A/D conversion to memory. * The activation source can be selected from among software, external trigger (falling edge), and timer (rising edge). * Register list A/D control status register lower/upper (ADCS0/ADCS1) bit 7 6 5 4 3 Address : 000040H MD1 MD0
( R/W ) ( R/W ) 14 INT ( R/W ) () 13 INTE ( R/W ) () 12 PAUS ( R/W ) () 11 STS1 ( R/W )
2 () 10 STS0 ( R/W )
1 () 9 STRT (W)
0
Reserved
Initial Value 00 - - - - - 0B
( R/W ) 8
Reserved
bit Address : 000041H
15 BUSY ( R/W )
Initial Value 00000000B
( R/W )
A/D data register lower/upper (ADCR0/ADCR1) bit 7 6 5 Address : 000042H D7 D6 D5
(R) (R) 14 ST1 (W) (R) 13 ST0 (W)
4 D4 (R) 12 CT1 (W)
3 D3 (R) 11 CT0 (W)
2 D2 (R) 10 ()
1 D1 (R) 9 D9 (R)
0 D0 (R) 8 D8 (R)
Initial Value XXXXXXXXB
bit Address : 000043H
15 S10 ( R/W )
Initial Value 00101XXXB
A/D conversion channel selection register (ADMR) bit 15 14 13 12 Address : 000045H ANS3 ANS2 ANS1 ANS0
( R/W ) ( R/W ) ( R/W ) ( R/W )
11 ANE3
10 ANE2
9 ANE1 ( R/W )
8 ANE0 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
70
MB90330A Series
* Block Diagram
AVCC AVRH AVSS
Conversion channel selection ADMR
D/A converter
MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
Sequential comparison register
Input circuit Sample & hold circuit
Data register
Decoder
ADCR0, ADCR1
ADTG
Trigger start Timer start
A/D control status register upper A/D control status register lower ADCS0, ADCS1
Timer (PPG1 output)
Operating clock Prescaler
Data bus
Comparator
71
MB90330A Series
13. DTP/External interrupt circuit
DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external interrupt input terminal (INT7 to INT0) , and outputs the interrupt request. * DTP/External interrupt circuit function The DTP/External interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (INT7 to INT0). If CPU accepts the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS. And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (DTP function) performed by EI2OS. * Overview of DTP/External interrupt circuit External interrupt Input pin DTP function
8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK, P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0) The detection level or the type of the edge for each terminal can be set in the request level setting register (ELVR). Input of H level/L level/rising edge/falling edge. #18 (12H), #20 (14H), #22 (16H), #24 (18H) Enabling/disabling the interrupt request output using the DTP/interrupt enable register (ENIR) Holding the interrupt causes using the DTP/interrupt cause register (EIRR) Disable EI2OS (ICR: ISE="0") Branched to the interrupt handling routine Enable EI2OS (ICR: ISE="1") After an automatic data transfer by EI2OS, branched to the interrupt handling routine
Interrupt source Interrupt number Interrupt control Interrupt flag Process setting Process
72
MB90330A Series
* Register list DTP/Interrupt enable register (ENIR) bit 7 6 Address : 00003CH EN7 EN6
(R/W) (R/W)
5 EN5 (R/W)
4 EN4 (R/W)
3 EN3 (R/W)
2 EN2 (R/W)
1 EN1 (R/W)
0 EN0 (R/W)
Initial Value 00000000B
DTP/Interrupt source register (EIRR) bit 15 14 Address : 00003DH ER7 ER6
(R/W) (R/W)
13 ER5 (R/W)
12 ER4 (R/W)
11 ER3 (R/W)
10 ER2 (R/W)
9 ER1 (R/W)
8 ER0 (R/W)
Initial Value 00000000B
Request level setting register (ELVR) bit 7 6 Address : 00003EH LB3 LA3
(R/W) (R/W)
5 LB2 (R/W)
4 LA2 (R/W)
3 LB1 (R/W)
2 LA1 (R/W)
1 LB0 (R/W)
0 LA0 (R/W)
Initial Value 00000000B
bit Address : 00003FH
15 LB7 (R/W)
14 LA7 (R/W)
13 LB6 (R/W)
12 LA6 (R/W)
11 LB5 (R/W)
10 LA5 (R/W)
9 LB4 (R/W)
8 LA4 (R/W)
Initial Value 00000000B
73
MB90330A Series
* Block Diagram
Request level setting register (ELVR)
LB7 LA7 2 LB6 LA6 2 LB5 LA5 2 LB4 LA4 2 LB3 LA3 2 LB2 LA2 2 LB1 LA1 2 LB0 LA0 2
Pin
P67/INT7/ SDA0
Selector
DTP/external interrupt input detection circuit
Selector
Pin
P60/INT0
Pin
P66/INT6/ SCL0
Selector
Selector
Pin
P61/INT1
Internal data bus
Pin
P65/INT5/ PWC
Selector
Selector
Pin
P62/INT2/ SIN
Pin
P64/INT4/ SCK DTP/interrupt source register (EIRR)
Selector
Selector
Pin
P63/INT3/ SOT
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Interrupt request signal
#18(12H)* #20(14H)* #22(16H)*
DTP/interrupt enable register (ENIR)
#24(18H)*
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
* : Interrupt number
74
MB90330A Series
14. Interrupt controller
The interrupt control register is located inside the interrupt controller; it exists for every I/O having an interrupt function. This register has the following functions. * Setting of the interrupt levels of relevant resources * Register list Interrupt control register (ICR01, ICR03, ICR05, ICR07, ICR09, ICR11, ICR13, ICR15) bit 15 14 13 12 11 10 9 8 Address : ICR01 : 0000B1H ICR03 : 0000B3H ICS3 ICS2 ICS1 ICS0 IL2 IL1 IL0 ISE ICR05 : 0000B5H (W) (W) (W) ( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ICR07 : 0000B7H ICR09 : 0000B9H ICR11 : 0000BBH ICR13 : 0000BDH ICR15 : 0000BFH Interrupt control register (ICR00, ICR02, ICR04, ICR06, ICR08, ICR10, ICR12, ICR14) bit 7 6 5 4 3 2 1 0 Address : ICR00 : 0000B0H ICS3 ICS2 ICS1 ICS0 IL2 IL1 IL0 ISE ICR02 : 0000B2H ICR04 : 0000B4H (W) (W) (W) ( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ICR06 : 0000B6H ICR08 : 0000B8H ICR10 : 0000BAH ICR12 : 0000BCH ICR14 : 0000BEH
Initial Value 00000111B
Initial Value 00000111B
Note : Do not access interrupt control registers using any read modify write instruction because it causes a malfunction. * Block Diagram
3 IL 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IL 1 IL 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 32
Interrupt request (peripheral resource)
F2MC-16LX bus
Determine priority of interrupt
3
(CPU) Interrupt level
75
MB90330A Series
15. DMAC
DMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features. * Performs automatic data transfer between the peripheral resource (I/O) and memory * The program execution of CPU stops in the DMA start-up * Capable of selecting whether to increment the transfer source and destination addresses * DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and descriptor. * A STOP request is available for stopping DMA transfer from the resource. Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller. * Register list DMA enable register upper (DERH) bit 15 14 Address : 0000ADH EN15 EN14
( R/W ) ( R/W ) 13 EN13 ( R/W ) 12 EN12 ( R/W ) 11 EN11 ( R/W ) 10 EN10 9 EN9 8 EN8 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
DMA enable register lower (DERL) bit 7 6 Address : 0000ACH EN7 EN6
( R/W ) ( R/W )
5 EN5 ( R/W )
4 EN4 ( R/W )
3 EN3 ( R/W )
2 EN2
1 EN1
0 EN0 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
DMA stop status register (DSSR) bit 7 6 Address : 0000A4H STP7 STP6
STP15 ( R/W )
STP14
5 STP5 STP13 ( R/W )
4 STP4 STP12 ( R/W )
3 STP3 STP11 ( R/W )
2 STP2 STP10
1 STP1 STP9
0 STP0 STP8 ( R/W )
Initial Value 00000000B *
( R/W )
( R/W ) ( R/W )
DMA status register upper (DSRH) bit 15 14 13 12 11 10 Address : 00009DH DTE15 DTE14 DTE13 DTE12 DTE11 DTE10
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
9 DTE9
8 DTE8 ( R/W )
Initial Value 00000000B
( R/W ) ( R/W )
DMA status register lower (DSRL) bit 7 6 Address : 00009CH DTE7 DTE6
( R/W ) ( R/W )
5 DTE5 ( R/W )
4 DTE4 ( R/W )
3 DTE3 ( R/W )
2 DTE2
1 DTE1
0 DTE0
Initial Value 00000000B
( R/W ) ( R/W ) ( R/W )
DMA descriptor channel specification register (DCSR) bit 15 14 13 12 11 10 9 8 Address : 00009BH Reserved Reserved Reserved DCSR3 DCSR2 DCSR1 DCSR0 STP
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
* : The DSSR is lower when the STP bit of DCSR in the DSSR is "0". The DSSR is upper when the STP bit of DCSR in the DSSR is "1". (Continued) 76
MB90330A Series
(Continued) DMA buffer address pointer lower 8-bit (DBAPL) bit 7 6 5 4 3 2 1 0 Address : 007920H DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA buffer address pointer middle 8-bit (DBAPM) bit 15 14 13 12 11 10 9 8 Address : 007921H DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA buffer address pointer upper 8-bit (DBAPH) bit 7 6 5 4 3 2 1 0 Address : 007922H DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH
( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA control register (DMACS) bit 15 Address : 007923H RDY2
( R/W )
14 RDY1 ( R/W )
13 BYTEL ( R/W )
12 IF ( R/W )
11 BW ( R/W )
10 BF
9 DIR
8 SE ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
DMA I/O register address pointer lower 8-bit (DIOAL) bit 7 6 5 4 Address : 007924H A07 A06 A05 A04
( R/W ) ( R/W ) ( R/W ) ( R/W )
3 A03
2 A02
1 A01 ( R/W )
0 A00 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
DMA I/O register address pointer upper 8-bit (DIOAH) bit 15 14 13 12 Address : 007925H A15 A14 A13 A12
( R/W ) ( R/W ) ( R/W ) ( R/W )
11 A11 ( R/W )
10 A10
9 A09
8 A08 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
DMA data counter lower 8-bit (DDCTL) bit 7 6 Address : 007926H B07 B06
( R/W ) ( R/W )
5 B05 ( R/W )
4 B04 ( R/W )
3 B03 ( R/W )
2 B02
1 B01
0 B00 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
DMA data counter upper 8-bit (DDCTH) bit 15 14 Address : 007927H B15 B14
( R/W ) ( R/W )
13 B13 ( R/W )
12 B12 ( R/W )
11 B11 ( R/W )
10 B10
9 B09
8 B08 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
Note : The above register is switched for each channel depending on the DCSR.
77
MB90330A Series
16. External bus pin control circuit
The external bus pin control circuit controls external bus pins to extend the CPU address and data buses to externals. * Register list * Automatic ready function selection register (ARSR) bit 15 14 13 12 Address : 0000A5H
ICR1 (W) ICR0 (W) HMR1 (W)
11 ()
10 ()
9 LMR1 (W)
8 LMR0 (W)
HMR0 (W)
Initial Value 0011- - 00B
* External address output control register (HACR) bit 7 6 5 Address : 0000A6H
E23 (W) E22 (W) E21 (W)
4 E20 (W)
3 E19 (W)
2 E18 (W)
1 E17 (W)
0 E16 (W)
Initial Value ********B
* Bus control signal selection register (EPCR) bit 15 14 13 Address : 0000A7H
CKE (W) RYE (W)
12
11
10 (W)RE (W)
9 LMBS (W)
8 ()
HDE (W)
Reserved HMBS (W) (W)
Initial Value 1000*10 -B
W :Write only - :Unused * :"1" or "0"
* Block Diagram
P5 P2 P3 P4 P5
P0
P1
P0 data
P0 direction
P0
RB
Data control
Address control
Access control
Access control
78
MB90330A Series
17. Address matching detection function
When the address is equal to the value set in the address detection register, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the program patch function is enabled. 2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code. * Register list * Program address detect register 0 to 2 (PADR0) PADR0 (lower) bit
7 6 5
4
3
2
1
0
Address : 001FF0H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
PADR0 (middle)
bit
15
14
13
12
11
10
9
8
Address : 001FF1H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
PADR0 (upper)
bit
7
6
5
4
3
2
1
0
Address : 001FF2H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
* Program address detect register 3 to 5 (PADR1) PADR1 (lower) bit
15 14 13
12
11
10
9
8
Address : 001FF3H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
PADR1 (middle)
bit
7
6
5
4
3
2
1
0
Address : 001FF4H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
PADR1 (upper)
bit
15
14
13
12
11
10
9
8
Address : 001FF5H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial Value XXXXXXXXB
* Program address detection control status register (PACSR) PACSR bit
7 6 5 4
3
2
Reserved
1
0
Address : 00009EH
Reserved Reserved Reserved Reserved
ADIE (R/W)
ADDE Reserved (R/W) (R/W)
Initial Value 00000000B
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
R/W : Readable and Writable X : Undefined
79
MB90330A Series
18. Delay interrupt generator module
The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware interrupt can be generated by software. * Delay interrupt generator module function Function and control * Setting the R0 bit in the delayed interrupt request generation/release register to 1 (DIRR: R0 = 1) generates a delayed interrupt request. * Setting the R0 bit in the delayed interrupt request generation/release register to 0 (DIRR: R0 = 0) cancels the delayed interrupt request. No setting of permission register is provided. Set in bit R0 of the delayed interrupt request generation /clear register (DIRR : R0) Not ready for extended intelligent I/O service (EI2OS).
Interrupt source
Interrupt control Interrupt flag EI OS support * Block Diagram
2
Internal data bus

R0
Delay interrupt factor generation/release register(DIRR) : Undefined
S Interrupt request R latch
Interrupt request signal
80
MB90330A Series
19. ROM mirror function selection module
The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read by accessing bank 00. * ROM mirroring function selection module function Description Mirror setting address Interrupt source EI2OS support * Block Diagram ROM mirror function selection register (ROMM)

Reserved
FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in the 00 bank. None. Not ready for extended intelligent I/O service (EI2OS) .
MI
Address Internal data bus FF bank Address area 00 bank
Data
ROM
81
MB90330A Series
20. Low power consumption (standby) mode
The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode. * CPU operation mode and functional description CPU Operation operating mode clock Normal run Sleep
Description
The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of oscillator clock (HCLK) frequency. Only peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) .
PLL clock
Time-base Only the time-base timer operates at the clock frequency obtained by PLL multiplicatimer tion of the oscillator clock (HCLK) frequency. Stop Normal run Sleep The CPU and peripheral resources are suspended with the oscillator clock stopped. The CPU and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.
Main clock
Time-base Only the time-base timer operates at the clock frequency obtained by dividing the timer oscillator clock (HCLK) frequency by two. Stop Normal run Sleep Watch mode Stop CPU intermittent operation mode * Register list Low power consumption mode control register (LPMCR) bit 7 6 5 4 3 Address : 0000A0H STP SLP SPL RST TMD
(W) (W) ( R/W ) (W) ( R/W )
The CPU and peripheral resources are suspended with the oscillator clock stopped. The CPU and peripheral resources operate at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. Only peripheral resources operate at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. Only the watch timer operates at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. The CPU and peripheral resources are suspended with the sub clock stopped. The halved or PLL-multiplied oscillator clock (HCLK) frequency or the sub clock (SCLK) frequency is used for operation while being decimated in a certain period.
Sub clock
Normal run
2 CG1
1 CG0
0
Reserved
Initial Value 00011000B
( R/W ) ( R/W )
( R/W )
82
MB90330A Series
21. Clock
The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation is referred to as PLL clock. * Register list Clock selection register (CKSCR) bit 15 14 Address : 0000A1H SCM MCM
(R) (R)
13 WS1 ( R/W )
12 WS0 ( R/W )
11 SCS ( R/W )
10 MCS ( R/W )
9 CS1 ( R/W )
8 CS0 ( R/W )
Initial Value 11111100B
83
MB90330A Series
22. 3 Mbits flash memory
The description that follows applies to the flash memory built in the MB90F334A; it is not applicable to evaluation ROM or MASK ROM. The flash memory is located in bank FF in the CPU memory map. * Function to flash memory Description Memory capacity Memory configuration Sector configuration Sector protect function Program algorithm 3072 Kbits (384 Kbytes) 384 Kwords x 8 bits/192 Kwords x 16 bits 64 Kbytes x 5 + 32 Kbytes + 8 Kbytes x 2 + 16 Kbytes Possibility that set up with a recommendation parallel writer Automatic program algorithm (Embedded Algorithm : Similar to MBM29LV400TC) * Compatibility with the JEDEC standard-type command * Built-in deletion pause/deletion resume function * Detection of programming/erasure completion using data polling and the toggle bit * Capable of erasing data sector by sector (in arbitrary combination of sectors) At least 10000 times guaranteed * Parallel programmer available for programming and erasure (Flash Support Group, Inc. : AF9708, AF9709, AF9709B) * Can be written and erased using a dedicated serial writer (Yokogawa Digital Computer Corporation : AF220/AF210/AF120/AF110) * Write/delete operation by program execution Programming/erasure completion sources Not ready for expanded intelligent I/O service (EI2OS).
Operation command
Program/Erase cycle
How to program and erase memory
Interrupt source EI2OS supports
84
MB90330A Series
* Sector configuration of flash memory
Flash Memory CPU address Writer address *
Prohibited
SA0 (64 Kbytes) SA1 (64 Kbytes) F80000H F8FFFFH F90000H F9FFFFH FA0000H FAFFFFH FB0000H SA2 (64 Kbytes) FBFFFFH FC0000H FCFFFFH FD0000H FDFFFFH FE0000H FEFFFFH FF0000H SA5 (32 Kbytes) SA6 (8 Kbytes) SA7 (8 Kbytes) FF7FFFH FF8000H FF9FFFH FFA000H FFBFFFH FFC000H SA8 (16 Kbytes) FFFFFFH 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 77FFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH
Prohibited
SA3 (64 Kbytes) SA4 (64 Kbytes)
* : The writer address is relative to the CPU address when data is programmed into flash memory by a parallel programmer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
* Register list Flash memory control status register (FMCS) bit 7 6 5 Address : 0000AEH INTE RDYINT WE
( R/W ) ( R/W ) ( R/W )
4 RDY (R)
3
Reserved
2
1
0 LPM0 ( R/W )
LPM1 Reserved ( R/W ) (W)
Initial Value 000X0000B
(W)
85
MB90330A Series
* Standard configuration for Fujitsu Microelectronics standard serial on-board writing The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corporation is used for Fujitsu Microelectronics standard serial on-board writing.
Host interface cable (AZ201)
General-purpose common cable (AZ210)
RS232C
Flash microcontroller programmer + Memory card
CLK synchronous serial
MB90F334A user system
Can operate stand alone
Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the AF220, AF210, AF120 and AF110 flash microcontroller programmer, general-purpose common cable for connection (AZ210) and connectors. * Pins Used for Fujitsu Microelectronics Standard Serial On-board Programming Pin Function Description The device enters the serial program mode by setting MD2=1, MD1=1 and MD0 =0. Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. Input a Low level to P60 and a High level to P61. UART0 is used as CLK synchronous mode. In program mode, the pins used for the UART0 CLK synchronous mode are SIN0, SOT0 and SCK0. When supplying the write voltage (MB90F334A : 3.3 V 0.3 V) from the user system, connection with the flash microcontroller programmer is not necessary. When connecting, do not short-circuit with the user power supply. Share GND with the flash microcontroller programmer. MD2, Mode input pins MD1, MD0 X0, X1 Oscillation pins Programming program start pins Reset input pin Serial data input pins. Serial data output pin Serial clock input pin
P60, P61 RST SIN0 SOT0 SCK0
VCC
Power source input pin
VSS
GND Pin
86
MB90330A Series
The control circuit shown in the figure is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcontroller programmer. * Control circuit AF220, AF210, AF120, AF110 program control pin
10 k
MB90F334A program control pin
AF220, AF210, AF120, AF110, /TICS pin User
The MB90F334A serial clock frequency that can be input is determined by the following expression: Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used. Inputable serial clock frequency = 0.125 x oscillation clock frequency. * Maximum serial clock frequency Maximum serial clock Oscillation frequency acceptable to the clock frequency flash microcontroller At 6 MHz 750 kHz Maximum serial clock frequency that can be set with the AF220, AF210, AF120 or AF110 500 kHz Maximum serial clock frequency that can be set with the AF200 500 kHz
* System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa Digital
Computer Corporation)
Part number AF220/AC4P Unit AF210/AC4P AF120/AC4P AF110/AC4P AZ221 AZ210 FF201 AZ290 /P4 Model with internal Ethernet interface Standard model
Function /100 V to 220 V power adapter /100 V to 220 V power adapter /100 V to 220 V power adapter /100 V to 220 V power adapter
Single key internal Ethernet interface mode Single key model PC/AT RS232C cable for writer Standard target probe (a) length : 1 m
Control module for Fujitsu Microelectronics F2MC-16LX flash microcontroller control module Remote controller 4 Mbytes PC Card (option) Flash memory capacity to 512 Kbytes correspondence
Contact to : Yokogawa Digital Computer Corporation TEL : 81-423-33-6224 Note : The AF200 flash microcontroller programmer is a retired product, but it can be supported using control module FF201.
87
MB90330A Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage*
1
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.5 VSS + 4.0 VSS + 4.5 +2.0 20 10 43 4 15/4.5 100 50 - 10 - 43 -4 -15/-4.5 - 100 - 50 340 + 85 + 150 + 125
Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C *9 *9
Remarks
AVCC AVRH
VCC AVCC*2 AVCC AVR 0 V*3 *4 N-ch open-drain (Withstand voltage of 5 V I/O)*5 USB I/O *4 USB I/O *6 *6 Other than USB I/O*7 USB I/O*7 *8 USB-IO (Full speed/ Low speed) *8
Input voltage*1
VI
VSS - 0.3 - 0.5
Output voltage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current
VO ICLAMP ICLAMP IOL1 IOL2 IOLAV1
VSS - 0.3 - 0.5 - 2.0 - 40 - 55 - 55
"L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current
IOLAV2 IOL IOLAV IOH1 IOH2 IOHAV1
Other than USB I/O*7 USB I/O*7 *8 USB-IO (Full speed/ Low speed) *8
"H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature
IOHAV2 IOH IOHAV Pd TA Tstg
USB I/O
*1 : The parameter is based on VSS = AVSS = 0.0 V. *2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on. *3 : Be careful not to let AVRH exceed AVcc. *4 : VI and VO must not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST (Continued) 88
MB90330A Series
(Continued) *6 : * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, P90 to P95, PB5, PB6 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM, HVP, HVM, UTEST, HCON * Sample recommended circuits: * Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V)
N-ch VCC P-ch
R
*7 : A peak value of an applicable one pin is specified as a maximum output current. *8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
89
MB90330A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Value Min 3.0 Power supply voltage VCC VIH VIHS1 Input "H" voltage VIHS2 VIHM VIHUSB VIL Input "L" voltage VILS VILM VILUSB Differential input sensitivity Differential common mode input voltage range Operating temperature VDI 2.7 1.8 0.7 VCC 0.8 VCC 0.8 VCC VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS 0.2 Max 3.6 3.6 3.6 VCC + 0.3 VCC + 0.3 VSS + 5.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.8 2.5 + 85 + 70 Unit V V V V V V V V V V V V V Remarks At normal operation (when using USB) At normal operation (when not using USB) Hold state of stop operation CMOS input pin CMOS hysteresis input pin N-ch open-drain (Withstand voltage of 5 V I/O)* MD pin input USB pin input CMOS input pin CMOS hysteresis input pin MD pin input USB pin input USB pin input
VCM
0.8 - 40 0
V C C
USB pin input When not using USB When using USB
TA
* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
90
MB90330A Series
3. DC Characteristics
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Value Unit Min Typ Max VCC - 0.5 2.8 Vss 0 Vcc 3.6 Vss + 0.4 0.3 V V V V Remarks
Output "H" voltage
Output "L" voltage
Input leak current
Output pins other than P60 to P67, P96, VOH PA0 to PA7, PB0 to PB4, HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM Output pins other than VOL HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM Output pins other than P60 to P67, P96, PA0 to PA7, IIL PB0 to PB4, HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM
IOH = - 4.0 mA RL = 15 k 5% IOL = 4.0 mA RL = 1.5 k 5% VCC = 3.3 V, Vss < VI < VCC
- 10
+ 10
A
-5 25
50 0.1 75 65 70 60
+5 100 10 85 75 80 70
A k A mA MB90F334A mA MB90333A mA MB90F334A mA MB90333A
Pull-up VCC = 3.3 V, RPULL P00 to P07, P10 to P17 resistance TA = + 25 C Open drain P60 to P67, P96, output ILIOD PA0 to PA7, PB0 to PB4 current VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At USB operating (USTP = 0) ICC VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At non-operating USB (USTP = 1) VCC = 3.3 V, Power Internal frequency 24 MHz, ICCS supply VCC At sleep mode current VCC = 3.3 V, Internal frequency 24 MHz, At timer mode ICTS VCC = 3.3 V, Internal frequency 3 MHz, At timer mode VCC = 3.3 V, Internal frequency 8 kHz, ICCL At sub clock operation, (TA = +25 C)
27
40
mA
3.5
10
mA
1
2
mA
25
150
A (Continued)
91
MB90330A Series
(Continued) (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions VCC = 3.3 V, Internal frequency 8 kHz, At sub clock, At sleep operating, (TA = + 25 C) VCC ICCT VCC = 3.3 V, Internal frequency 8 kHz, Watch mode, (TA = + 25 C) TA = + 25 C, At stop Other than AVcc, AVss, Vcc, Vss RST DVP, DVM HVP, HVM Value Min Typ Max Unit Remarks
ICCLs Power supply current
10
50
A
1.5
40
A
ICCH Input capacitance Pull-up resistor USB I/O output impedance CIN Rup ZUSB
25 3
1 5 50
40 15 100 14
A pF k
Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are N-ch open-drain pins usually used as CMOS.
92
MB90330A Series
4. AC Characteristics
(1)Clock input timing Parameter (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) SymPin name bol fCH fCL Clock cycle time tHCYL tLCYL PWH PWL PWHL PWLL tcr tcf fCP fCPL tCP tCPL X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min 6 166.7 10 3 42 Typ 6 32.768 166.7 30.5 15.2 8.192 122.1 Max 24 41.7 5 24 333 Unit Remarks
MHz When oscillator is used MHz External clock input kHz ns ns s ns s ns At external clock A reference duty ratio is 30% to 70%. When oscillator is used External clock input
Clock frequency
Input clock pulse width
Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
MHz When main clock is used kHz When sub clock is used ns s When main clock is used When sub clock is used
* Clock Timing
tHCYL 0.8 VCC
X0
0.2 VCC PWH tcf tLCYL 0.8 VCC PWL tcr
X0A
0.2 VCC PWHL tcf PWLL tcr
93
MB90330A Series
* PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency PLL operation guarantee range
3.6
Power voltage VCC (V)
3.0 2.7
Normal Operation Assurance Range
3 6 12 24
Internal clock FCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.
Relation between internal operation clock frequency and external clock frequency
24
Multiplied by 4
Internal clock FCP (MHz)
12
Multiplied by 2
6
External clock Multiplied by 1
3
6
24
External clock Fc (MHz)
94
MB90330A Series
The AC standards assume the following measurement reference voltages. * Input signal waveform * Output signal waveform Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Hysteresis input/other than MD input pin
0.7 VCC 0.3 VCC
95
MB90330A Series
(2)Clock output timing (VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Unit Remarks Min Max tCP tCP/2 - 15 CLKCLK tCHCL CLK VCC = 3.0 V to 3.6 V tCP/2 - 20 tCP/2 - 64 Note : tCP : Refer to " (1) Clock input timing". tCP/2 + 15 tCP/2 + 20 tCP/2 + 64 ns ns ns ns At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz
Parameter Cycle time
Symbol Pin name tCYC CLK
Conditions
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
96
MB90330A Series
(3) Reset Pin name (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Conditions Unit Remarks Min Max At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode At stop mode, At sub clock mode, At sub sleep mode, At watch mode
Parameter
Symbol
500 Reset input time tRSTL RST Oscillation time of oscillator* + 500 ns
ns
s
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock.
* During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 Vcc 0.2 Vcc
* During stop mode, sub clock mode, sub-sleep mode and watch mode
tRSTL
RST
0.2 Vcc 0.2 Vcc
X0
90% of amplitude
Internal operation clock
Oscillation time of oscillator
500 ns
Oscillation stabilization wait time
Execute instruction
Internal reset
97
MB90330A Series
(4) Power-on reset (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to +85 C) Parameter Power supply rising time Power supply shutdown time Symbol Pin name Conditions tR tOFF VCC VCC 1 ms Value Min 0.05 Max 30 Unit ms Waiting time until power-on Remarks
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Notes : * VCC must be lower than 0.2 V before the power supply is turned on. * The above standard is a value for performing a power-on reset. * In the device, there are internal registers which is initialized only by a power-on reset. When the initialization of these items is expected, turn on the power supply according to the standards. * Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms or less.
3.0 V VSS
RAM data hold
98
MB90330A Series
(5) UART0, UART1, UART2, UART3 I/O extended serial timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Serial clock H pulse width Serial clock L pulse width SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx, SINx SCKx, SINx External shift clock mode output pin is : CL = 80 pF + 1TTL Internal shift clock mode output pin is : CL = 80 pF + 1TTL Conditions Value Min 8 tCP - 80 100 60 4 tCP 4 tCP 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns
Notes : * Above rating is the case of CLK synchronous mode. * CL is a load capacitance value on pins for testing. * tCP : Refer to " (1) Clock input timing".
99
MB90330A Series
* Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
100
MB90330A Series
(6) I2C timing Parameter SCL clock frequency (Repeat) [start] condition hold time SDA SCL SCL clock "L" width SCL clock "H" width Repeat [start] condition setup time SCL SDA Data hold time SCL SDA (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Symbol Conditions Unit Min Max fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT Power-supply voltage of external pull-up resistor at 5.0 V. fCP*1 20 MHz, R = 1.2 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. fCP*1 20 MHz, R = 1.0 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 5.0 V. fCP*1 > 20 MHz, R = 1.2 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. fCP*1 > 20 MHz, R = 1.0 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 5.0 V. R = 1.2 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. R = 1.0 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 5.0 V. R = 1.2 k, C = 50 pF*2 Power-supply voltage of external pull-up resistor at 3.6 V. R = 1.0 k, C = 50 pF*2 0 4.0 4.7 4.0 4.7 0 100 3.45*3 kHz s s s s s
250*4
Data setup time SDA SCL
tSUDAT
ns
200*4
[Stop] condition setup time SCL SDA Bus free time between [stop] condition and [start] condition
tSUSTO
4.0
s
tBUS
4.7
s
*1 : fCP is internal operating clock frequency. Refer to " (1) Clock input timing". *2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance. *3 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *4 : Refer to "* Note of SDA, SCL set-up time".
101
MB90330A Series
* Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. *Timing definition
SDA
tLOW tSUDAT tHDSTA tBUS
SCL
tHDSTA tHDDAT tHIGH tSUSTA tSUSTO
102
MB90330A Series
(7) Timer input timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Pin name Conditions Unit Min Max FRCK, INx, TINx, PWC 4 tCP ns
Parameter
Symbol tTIWH tTIWL
Input pulse width
Note : tCP : Refer to " (1) Clock input timing".
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
PWC TINx INx FRCK
tTIWH
tTIWL
(8) Timer output timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Symbol Pin name Conditions Unit Min Max TOTx, tTO PPGx, OUTx 30 ns
Parameter CLKTOUT change time PPG0 to PPG5 change time OUT0 to OUT3 change time
CLK
2.4 V
tTO
PPGx OUTx
2.4 V 0.8 V
(9) Trigger input timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Value Pin name Conditions Unit Remarks Min Max INTx, ADTG 5 tCP 1 ns s At normal operating In Stop mode
Parameter Input pulse width
Symbol tTRGH tTRGL
Note : tCP : Refer to " (1) Clock input timing".
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
INTx ADTGx
tTRGH
tTRGL
103
MB90330A Series
(10) Bus read timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Value SymPin name Conditions Unit Remarks bol Min Max tCP/2 - 15 ALE pulse width tLHLL ALE tCP/2 - 20 tCP/2 - 35 Valid addressALEtime ALEAddress valid time Valid addressRDtime Valid addressvalid data input RD pulse width RDvalid data input RDdata hold time RDALEtime RDaddress valid time Valid addressCLKtime RDCLKtime ALERDtime tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL Address, ALE ALE, Address RD, Address Address/ data RD RD, Data RD, Data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE tCP/2 - 17 tCP/2 - 40 tCP/2 - 15 tCP - 25 3 tCP/2 - 25 3 tCP/2 - 20 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 17 tCP/2 - 17 tCP/2 - 15 5 tCP/2 - 55 5 tCP/2 - 80 3 tCP/2 - 55 3 tCP/2 - 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns At fcp = 6 MHz At fcp = 6 MHz At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz
Parameter
Note : tCP : Refer to " (1) Clock input timing".
104
MB90330A Series
tAVCH 2.4 V
tRLCH 2.4 V
CLK
tRHLH
ALE
2.4 V tLHLL
2.4 V 0.8 V tRLRH
2.4 V
RD
2.4 V tAVLL tLLAX tLLRL 0.8 V
In multiplex mode
A23 to A16
2.4 V 0.8 V
tAVRL
tRLDV
tRHAX 2.4 V 0.8 V
tAVDV
tRHDX 0.7 VCC 0.7 VCC
AD15 to AD00
2.4 V
2.4 V
Address
0.8 V 0.8 V 0.3 VCC
Read data
0.3 VCC tRHAX
In non-multiplex mode
A23 to A00
2.4 V 0.8 V tRLDV tAVDV
2.4 V 0.8 V
tRHDX 0.7 VCC 0.7 VCC
D15 to D00
Read data
0.3 VCC 0.3 VCC
105
MB90330A Series
(11) Bus write timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Value Pin name Conditions Unit Remarks Min Max Address, WR WRL, WRH Data, WR WR, Data WR, Address WR, ALE WR, CLK tCP - 15 3 tCP/2 - 25 3 tCP/2 - 20 3 tCP/2 - 15 10 20 30 tCP/2 - 10 tCP/2 - 15 tCP/2 - 17 ns ns ns ns ns ns ns ns ns ns At fcp = 24 MHz At fcp = 12 MHz At fcp = 6 MHz At fcp = 24 MHz At fcp = 12 MHz
Parameter Valid addressWR time WR pulse width Valid data outputWR time WRdata hold time
Symbol tAVWL tWLWH tDVWH
tWHDX
WRaddress valid time WRALEtime WRCLKtime
tWHAX tWHLH tWLCH
Note : tCP : Refer to " (1) Clock input timing".
tWLCH 2.4 V
CLK
tWHLH
ALE
tWLWH 2.4 V
2.4 V
WR (WRL, WRH)
0.8 V
In multiplex mode
A23 to A16
2.4 V 0.8 V
tAVWL
tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V 0.8 V tWHAX
AD15 to AD00
2.4 V 0.8 V
Address
2.4 V 0.8 V
Write data
In non-multiplex mode
A23 to A00
2.4 V 0.8 V tDVWH
2.4 V 0.8 V tWHDX 2.4 V 0.8 V
D15 to D00
2.4 V 0.8 V
Write data
106
MB90330A Series
(12) Ready input timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter RDY set-up time RDY hold time Symbol tRYHS tRYHH Pin name Conditions RDY Value Min 35 70 0 Max Unit ns ns ns fcp = 6 MHz Remarks
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS tRYHH
RDY wait not applied RDY wait applies (1cycle)
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC tRYHS
107
MB90330A Series
(13) Hold timing (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter Pin floating HAK time HAK pin valid time Symbol tXHAL tHAHV Pin name HAK HAK Conditions Value Min 30 tCP Max tCP 2 tCP Unit ns ns
Notes : * It takes one cycle or more for HAK to change after the HRQ pin is captured. * tCP : Refer to " (1) Clock input timing".
HAK
0.8 V tXHAL 2.4 V
2.4 V tHAHV
High-Z
2.4 V 0.8 V
Each pin
0.8 V
108
MB90330A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supplying current Interchannel disparity Symbol VOT VFST IAIN VAIN IA IAH IR IRH Pin name AN0 to AN15 AN0 to AN15 AN0 to AN15 AN0 to AN15 AVRH AVCC AVCC AVRH AVRH AN0 to AN15 Value Min AVSS - 1.5 LSB AVRH - 3.5 LSB 0 2.7 Typ AVSS + 0.5 LSB AVRH - 1.5 LSB 176 tCP*1 64 tCP*1 1.4 95 Max 10 3.0 2.5 1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB 10 AVRH AVCC 3.5 5 170 5 4 Unit bit LSB LSB LSB mV 1 LSB = AVRH/1024 mV ns ns A V V mA A A A LSB *2 *2 Remarks
*1 : tCP : Refer to " 4. AC Characteristics (1) Clock input timing". *2 : The current when the CPU is in stop mode and the A/D converter is not operating (For VCC = AVCC = AVRH = 3.3 V).
109
MB90330A Series
Notes : * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R
Analog input
C
Comparator During sampling : ON MB90333A MB90F334A MB90V330A R 1.9 k (Max) 1.9 k (Max) 1.9 k (Max) C 32.3 pF (Max) 25.0 pF (Max) 32.3 pF (Max)
Note : The values are reference values.
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k)
MB90333A/ MB90V330A MB90F334A
(External impedance = 0 k to 20 k)
MB90333A/ MB90V330A MB90F334A
100 90 80 70 60 50 40 30 20 10 0 0 5
20 18 16 14 12 10 8 6 4 2 0 0 1
External impedance [k]
10
15
20
25
30
35
External impedance [k]
2
3
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
* About errors As |AVRH| becomes smaller, values of relative errors grow larger.
110
MB90330A Series
A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter. Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH 3FEH 3FDH Digital output Actual conversion value 0.5 LSB {1 LSB x (N - 1) + 0.5 LSB}
004H 003H 002H 001H 0.5 LSB AVRL Analog input AVRH VNT (Measured value) Actual conversion value Theoretical characteristics
Total error for digital output N = 1 LSB (Theoretical value) =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVss [V] 1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V] VFST (Theoretical value) = AVR - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) H to NH
(Continued)
111
MB90330A Series
(Continued) Linearity error
3FFH 3FEH 3FDH Digital output Actual conversion value {1 LSB x (N - 1) + VOT } Digital output VFST (Measured value) (N + 1)H
Differential linearity error
Theoretical characteristics Actual conversion value
NH V (N + 1) T (Measured value) VNT (Measured value) (N - 2)H Actual conversion value
004H 003H 002H 001H AVRL
VNT (Measured value) Actual conversion value Theoretical characteristics VOT (Measured value) AVRH Analog input
(N - 1)H
AVRL Analog input
AVRH
Linearity error of = digital output N
VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 [LSB] [V]
[LSB]
Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = VFST - VOT 1022
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
112
MB90330A Series
6. USB characteristics
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 C to + 70 C) Parameter Input High level voltage Input Low level voltage Input characteristics Differential input sensitivity Differential common mode range Output High level voltage Output Low level voltage Cross over voltage Rise time Output characteristics Fall time Rising/falling time matching Output impedance Series resistance Symbol VIH VIL VDI VCM VOH VOL VCRS tFR tLR tFF tLF tRFM tRLM ZDRV RS Value Min 2.0 0.2 0.8 2.8 0.0 1.3 4 75 4 75 90 80 28 25 Max 0.8 2.5 3.6 0.3 2.0 20 300 20 300 111.11 125 44 30 Unit V V V V V V V ns ns ns ns % % Full Speed Low Speed Full Speed Low Speed (TFR/TFF) (TLR/TLF) Including Rs = 27 Recommended value = 27 at using USB* IOH = - 200 A IOL = 2 mA Remarks
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV. * Data signal timing (Full Speed) Rise time
DVP/HVP DVM/HVM
Vcrs 10% 90%
Fall time
90% 10%
tFR
tFF
* Data signal timing (Low Speed)
Rise time
HVP HVM
Vcrs 10% 90%
Fall time
90% 10%
tLR
tLF
113
MB90330A Series
* Load condition (Full Speed)
ZUSB DVP/HVP
RS = 27
Testing point
CL = 50 pF ZUSB DVM/HVM RS = 27
Testing point
CL = 50 pF
* Load condition (Low Speed)
ZUSB HVP
RS = 27
Testing point
CL = 50 pF to 150 pF ZUSB HVM RS = 27
Testing point
CL = 50 pF to 150 pF
114
MB90330A Series
7. Flash memory write/erase characteristics
Parameter Sector erase time Chip erase time Word (16-bit width) programming time Programming/erase cycle Flash memory data retaining period Average TA = + 85 C TA = + 25 C VCC = 3.0 V Condition Value Min 10000 20 Typ 1 9 16 Max 15 3600 Unit s s s cycle year * Remarks Excludes 00H programming prior to erasure. Excludes 00H programming prior to erasure. Except for over head time of system level
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C)
115
MB90330A Series
ORDERING INFORMATION
Part number MB90F334APFF MB90333APFF MB90F334APMC MB90333APMC MB90V330A Package 120-pin plastic LQFP (FPT-120P-M05) 120-pin plastic LQFP (FPT-120P-M21) 299-pin ceramic PGA (PGA-299C-A01) For evaluation Remarks
116
MB90330A Series
PACKAGE DIMENSIONS
120-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.40 mm 14.0 x 14.0 mm Gullwing Plastic mold 1.70 mm MAX 0.62 g P-LFQFP120-14x14-0.40
(FPT-120P-M05)
Code (Reference)
120-pin plastic LQFP (FPT-120P-M05)
16.000.20(.630.008)SQ
* 14.000.10(.551.004)SQ
90 61
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
91
60
0.08(.003)
Details of "A" part 1.50 -0.10
+0.20 +.008
(Mounting height)
INDEX
.059 -.004
120
31
"A"
0~8
LEAD No.
1
30
0.40(.016)
0.160.03 (.006.001)
0.07(.003)
M
0.1450.055 (.006.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
2003 FUJITSU LIMITED F120006S-c-4-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
117
MB90330A Series
(Continued)
120-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method M ounting height Weight 0.50 mm 16.0 x 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88 g P-LFQFP120-16x16-0.50
(FPT-120P-M21)
Code (Reference)
120-pin plastic LQFP (FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
18.000.20(.709.008)SQ
* 16.00 -0.10 .630 +.016 SQ -.004
90 61
+0.40
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX 0~8
120 31
"A" 0.100.05 (.004.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 .006
+0.05 -0.03 +.002 -.001
0.600.15 (.024.006)
C
2002 FUJITSU LIMITED F120033S-c-4-4
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
118
MB90330A Series
MAIN CHANGES IN THIS EDITION
Page 3 4 64 Section INTERNAL PERIPHERAL FUNCTION (RESOURCE) PRODUCT LINEUP PERIPHERAL RESOURCES 10. USB Function * Feature of USB function Change Results Changed as follows conform to USB2.0 Full Speed correspond to USB Full Speed
The vertical lines marked in the left side of the page show the changes
119
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Yan An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.

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